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Egea Canet, F. J. et al, Gadea, A., & Huyuk, T. (2015). Digital Front-End Electronics for the Neutron Detector NEDA. IEEE Trans. Nucl. Sci., 62(3), 1063–1069.
Abstract: This paper presents the design of the NEDA (Neutron Detector Array) electronics, a first attempt to involve the use of digital electronics in large neutron detector arrays. Starting from the front-end modules attached to the PMTs (PhotoMultiplier Tubes) and ending up with the data processing workstations, a comprehensive electronic system capable of dealing with the acquisition and pre-processing of the neutron array is detailed. Among the electronic modules required, we emphasize the front-end analog processing, the digitalization, digital pre-processing and communications firmware, as well as the integration of the GTS (Global Trigger and Synchronization) system, already used successfully in AGATA (Advanced Gamma Tracking Array). The NEDA array will be available for measurements in 2016.
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Barrientos, D., Bellato, M., Bazzacco, D., Bortolato, D., Cocconi, P., Gadea, A., et al. (2015). Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array. IEEE Trans. Nucl. Sci., 62(6), 3134–3139.
Abstract: In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.53% at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs.
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Marco-Hernandez, R., Bau, M., Ferrari, M., Ferrari, V., Pedersen, F., & Soby, L. (2017). A Low-Noise Charge Amplifier for the ELENA Trajectory, Orbit, and Intensity Measurement System. IEEE Trans. Nucl. Sci., 64(9), 2465–2473.
Abstract: A low-noise head amplifier has been developed for the extra low energy antiproton ring beam trajectory, orbit, and intensity measurement system at CERN. This system is based on 24 double-electrode electrostatic beam position monitors installed around the ring. A head amplifier is placed close to each beam position monitor to amplify the electrode signals and generate a difference and a sum signal. These signals are sent to the digital acquisition system, about 50 m away from the ring, where they are digitized and further processed. The beam position can be measured by dividing the difference signal by the sum signal while the sum signal gives information relative to the beam intensity. The head amplifier consists of two discrete charge preamplifiers with junction field effect transistor (JFET) inputs, a sum and a difference stage, and two cable drivers. Special attention has been paid to the amplifier printed circuit board design to minimize the parasitic capacitances and inductances at the charge amplifier stages to meet the gain and noise requirements. The measurements carried out on the head amplifier showed a gain of 40.5 and 46.5 dB for the sum and difference outputs with a bandwidth from 200 Hz to 75 MHz and an input voltage noise density lower than 400 pV/v Hz. Twenty head amplifiers have been already installed in the ring and they have been used to detect the first beam signals during the first commissioning stage in November 2016.
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Aliaga, R. J. (2017). Real-Time Estimation of Zero Crossings of Sampled Signals for Timing Using Cubic Spline Interpolation. IEEE Trans. Nucl. Sci., 64(8), 2414–2422.
Abstract: A scheme is proposed for hardware estimation of the location of zero crossings of sampled signals with subsample resolution for timing applications, which consists of interpolating the signal with a cubic spline near the zero crossing and then finding the root of the resulting polynomial. An iterative algorithm based on the bisection method is presented that obtains one bit of the result per step and admits an efficient digital implementation using fixed-point representation. In particular, the root estimation iteration involves only two additions, and the initial values can be obtained from finite impulse response (FIR) filters with certain symmetry properties. It is shown that this allows online real-time estimation of timestamps in free-running sampling detector systems with improved accuracy with respect to the more common linear interpolation. The method is evaluated with simulations using ideal and real timing signals, and estimates are given for the resource usage and speed of its implementation.
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Carrio, F. (2022). The Data Acquisition System for the ATLAS Tile Calorimeter Phase-II Upgrade Demonstrator. IEEE Trans. Nucl. Sci., 69(4), 687–695.
Abstract: The tile calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the large hadron collider (LHC). In 2025, the LHC will be upgraded leading to the high luminosity LHC (HL-LHC). The HL-LHC will deliver an instantaneous luminosity up to seven times larger than the LHC nominal luminosity. The ATLAS Phase-II upgrade (2025-2027) will accommodate the subdetectors to the HL-LHC requirements. As part of this upgrade, the majority of the TileCal on-detector and off-detector electronics will be replaced using a new readout strategy, where the on-detector electronics will digitize and transmit digitized detector data to the off-detector electronics at the bunch crossing frequency (40 MHz). In the counting rooms, the off-detector electronics will compute reconstructed trigger objects for the first-level trigger and will store the digitized samples in pipelined buffers until the reception of a trigger acceptance signal. The off-detector electronics will also distribute the LHC clock to the on-detector electronics embedded within the digital data stream. The TileCal Phase-II upgrade project has undertaken an extensive research and development program that includes the development of a Demonstrator module to evaluate the performance of the new clock and readout architecture envisaged for the HL-LHC. The Demonstrator module equipped with the latest version of the on-detector electronics was built and inserted into the ATLAS experiment. The Demonstrator module is operated and read out using a Tile PreProcessor (TilePPr) Demonstrator which enables backward compatibility with the present ATLAS Trigger and Data AcQuisition (TDAQ), and the timing, trigger, and command (TTC) systems. This article describes in detail the main hardware and firmware components of the clock distribution and data acquisition systems for the Demonstrator module, focusing on the TilePPr Demonstrator.
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