Tetrault, M. A., Oliver, J. F., Bergeron, M., Lecomte, R., & Fontaine, R. (2010). Real Time Coincidence Detection Engine for High Count Rate Timestamp Based PET. IEEE Trans. Nucl. Sci., 57(1), 117–124.
Abstract: Coincidence engines follow two main implementation flows: timestamp based systems and AND-gate based systems. The latter have been more widespread in recent years because of its lower cost and high efficiency. However, they are highly dependent on the selected electronic components, they have limited flexibility once assembled and they are customized to fit a specific scanner's geometry. Timestamp based systems are gathering more attention lately, especially with high channel count fully digital systems. These new systems must however cope with important singles count rates. One option is to record every detected event and postpone coincidence detection offline. For daily use systems, a real time engine is preferable because it dramatically reduces data volume and hence image preprocessing time and raw data management. This paper presents the timestamp based coincidence engine for the LabPET(TM), a small animal PET scanner with up to 4608 individual readout avalanche photodiode channels. The engine can handle up to 100 million single events per second and has extensive flexibility because it resides in programmable logic devices. It can be adapted for any detector geometry or channel count, can be ported to newer, faster programmable devices and can have extra modules added to take advantage of scanner-specific features. Finally, the user can select between full processing mode for imaging protocols and minimum processing mode to study different approaches for coincidence detection with offline software.
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Miñano, M. (2011). Radiation Hard Silicon Strips Detectors for the SLHC. IEEE Trans. Nucl. Sci., 58(3), 1135–1140.
Abstract: While the Large Hadron Collider (LHC) began taking data in 2009, scenarios for a machine upgrade to achieve a much higher luminosity are being developed. In the current planning, it is foreseen to increase the luminosity of the LHC at CERN around 2018. As radiation damage scales with integrated luminosity, the particle physics experiments will need to be equipped with a new generation of radiation hard detectors. This article reports on the status of the R&D projects on radiation hard silicon strips detectors for particle physics, linked to the Large Hadron Collider Upgrade, super-LHC (sLHC) of the ATLAS microstrip detector. The primary focus of this report is on measuring the radiation hardness of the silicon materials and the detectors under study. This involves designing silicon detectors, irradiating them to the sLHC radiation levels and studying their performance as particle detectors. The most promising silicon detector for the different radiation levels in the different regions of the ATLAS microstrip detector will be presented. Important challenges related to engineering layout, powering, cooling and reading out a very large strip detector are presented. Ideas on possible schemes for the layout and support mechanics will be shown.
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Carrio, F., Castillo Gimenez, V., Ferrer, A., Gonzalez, V., Higon-Rodriguez, E., Marin, C., et al. (2011). Optical Link Card Design for the Phase II Upgrade of TileCal Experiment. IEEE Trans. Nucl. Sci., 58(4), 1657–1663.
Abstract: This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol.
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DEPFET collaboration(Alonso, O. et al), Boronat, M., Esperante-Pereira, D., Fuster, J., Garcia, I. G., Lacasta, C., et al. (2013). DEPFET Active Pixel Detectors for a Future Linear e(+)e(-) Collider. IEEE Trans. Nucl. Sci., 60(2), 1457–1465.
Abstract: The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key principle, the integration of a first amplification stage in a detector-grade sensor material, can provide a comfortable signal to noise ratio of over 40 for a sensor thickness of 50-75 μm. ASICs have been designed and produced to operate a DEPFET pixel detector with the required read-out speed. A complete detector concept is being developed, including solutions for mechanical support, cooling, and services. In this paper, the status of the DEPFET R & D project is reviewed in the light of the requirements of the vertex detector at a future linear e(+)e(-) collider.
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Boronat, M., Marinas, C., Frey, A., Garcia, I., Schwenker, B., Vos, M., et al. (2015). Physical Limitations to the Spatial Resolution of Solid-State Detectors. IEEE Trans. Nucl. Sci., 62(1), 381–386.
Abstract: In this paper we explore the effect of delta-ray emission and fluctuations in the signal deposition on the detection of charged particles in silicon-based detectors. We show that these two effects ultimately limit the resolution that can be achieved by interpolation of the signal in finely segmented position-sensitive solid-state devices.
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Egea Canet, F. J. et al, Gadea, A., & Huyuk, T. (2015). A New Front-End High-Resolution Sampling Board for the New-Generation Electronics of EXOGAM2 and NEDA Detectors. IEEE Trans. Nucl. Sci., 62(3), 1056–1062.
Abstract: This paper presents the final design and results of the FADC Mezzanine for the EXOGAM (EXOtic GAMma array spectrometer) and NEDA (Neutron Detector Array) detectors. The measurements performed include those of studying the effective number of bits, the energy resolution using HP-Ge detectors, as well as timing histograms and discrimination performance. Finally, the conclusion shows how a common digitizing device has been integrated in the experimental environment of two very different detectors which combine both low-noise acquisition and fast sampling rates. Not only the integration fulfilled the expected specifications on both systems, but it also showed how a study of synergy between detectors could lead to the reduction of resources and time by applying a common strategy.
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Egea Canet, F. J. et al, Gadea, A., & Huyuk, T. (2015). Digital Front-End Electronics for the Neutron Detector NEDA. IEEE Trans. Nucl. Sci., 62(3), 1063–1069.
Abstract: This paper presents the design of the NEDA (Neutron Detector Array) electronics, a first attempt to involve the use of digital electronics in large neutron detector arrays. Starting from the front-end modules attached to the PMTs (PhotoMultiplier Tubes) and ending up with the data processing workstations, a comprehensive electronic system capable of dealing with the acquisition and pre-processing of the neutron array is detailed. Among the electronic modules required, we emphasize the front-end analog processing, the digitalization, digital pre-processing and communications firmware, as well as the integration of the GTS (Global Trigger and Synchronization) system, already used successfully in AGATA (Advanced Gamma Tracking Array). The NEDA array will be available for measurements in 2016.
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Barrientos, D., Bellato, M., Bazzacco, D., Bortolato, D., Cocconi, P., Gadea, A., et al. (2015). Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array. IEEE Trans. Nucl. Sci., 62(6), 3134–3139.
Abstract: In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.53% at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs.
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Gonzalez-Iglesias, D., Esperante, D., Gimeno, B., Boronat, M., Blanch, C., Fuster-Martinez, N., et al. (2021). Analytical RF Pulse Heating Analysis for High Gradient Accelerating Structures. IEEE Trans. Nucl. Sci., 68(2), 78–91.
Abstract: The main aim of this work is to present a simple method, based on analytical expressions, for obtaining the temperature increase due to the Joule effect inside the metallic walls of an RF accelerating component. This technique relies on solving the 1-D heat-transfer equation for a thick wall, considering that the heat sources inside the wall are the ohmic losses produced by the RF electromagnetic fields penetrating the metal with finite electrical conductivity. Furthermore, it is discussed how the theoretical expressions of this method can be applied to obtain an approximation to the temperature increase in realistic 3-D RF accelerating structures, taking as an example the cavity of an RF electron photoinjector and a traveling wave linac cavity. These theoretical results have been benchmarked with numerical simulations carried out with commercial finite-element method (FEM) software, finding good agreement among them. Besides, the advantage of the analytical method with respect to the numerical simulations is evidenced. In particular, the model could be very useful during the design and optimization phase of RF accelerating structures, where many different combinations of parameters must be analyzed in order to obtain the proper working point of the device, allowing to save time and speed up the process. However, it must be mentioned that the method described in this article is intended to provide a quick approximation to the temperature increase in the device, which of course is not as accurate as the proper 3-D numerical simulations of the component.
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Carrio, F. (2022). The Data Acquisition System for the ATLAS Tile Calorimeter Phase-II Upgrade Demonstrator. IEEE Trans. Nucl. Sci., 69(4), 687–695.
Abstract: The tile calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the large hadron collider (LHC). In 2025, the LHC will be upgraded leading to the high luminosity LHC (HL-LHC). The HL-LHC will deliver an instantaneous luminosity up to seven times larger than the LHC nominal luminosity. The ATLAS Phase-II upgrade (2025-2027) will accommodate the subdetectors to the HL-LHC requirements. As part of this upgrade, the majority of the TileCal on-detector and off-detector electronics will be replaced using a new readout strategy, where the on-detector electronics will digitize and transmit digitized detector data to the off-detector electronics at the bunch crossing frequency (40 MHz). In the counting rooms, the off-detector electronics will compute reconstructed trigger objects for the first-level trigger and will store the digitized samples in pipelined buffers until the reception of a trigger acceptance signal. The off-detector electronics will also distribute the LHC clock to the on-detector electronics embedded within the digital data stream. The TileCal Phase-II upgrade project has undertaken an extensive research and development program that includes the development of a Demonstrator module to evaluate the performance of the new clock and readout architecture envisaged for the HL-LHC. The Demonstrator module equipped with the latest version of the on-detector electronics was built and inserted into the ATLAS experiment. The Demonstrator module is operated and read out using a Tile PreProcessor (TilePPr) Demonstrator which enables backward compatibility with the present ATLAS Trigger and Data AcQuisition (TDAQ), and the timing, trigger, and command (TTC) systems. This article describes in detail the main hardware and firmware components of the clock distribution and data acquisition systems for the Demonstrator module, focusing on the TilePPr Demonstrator.
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