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Aliaga, R. J. (2017). Real-Time Estimation of Zero Crossings of Sampled Signals for Timing Using Cubic Spline Interpolation. IEEE Trans. Nucl. Sci., 64(8), 2414–2422.
Abstract: A scheme is proposed for hardware estimation of the location of zero crossings of sampled signals with subsample resolution for timing applications, which consists of interpolating the signal with a cubic spline near the zero crossing and then finding the root of the resulting polynomial. An iterative algorithm based on the bisection method is presented that obtains one bit of the result per step and admits an efficient digital implementation using fixed-point representation. In particular, the root estimation iteration involves only two additions, and the initial values can be obtained from finite impulse response (FIR) filters with certain symmetry properties. It is shown that this allows online real-time estimation of timestamps in free-running sampling detector systems with improved accuracy with respect to the more common linear interpolation. The method is evaluated with simulations using ideal and real timing signals, and estimates are given for the resource usage and speed of its implementation.
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Real, D., Calvo, D., Manzaneda, M., Diaz, A., Gozzini, S. R., Zornoza, J. D., et al. (2025). Novel Hybrid Low-Resource Field-Programmable-Gate-Array Time-to-Digital-Converter Architecture. IEEE Trans. Instrum. Meas., 74, 2000812–12pp.
Abstract: Time measurements are challenging in electronics given their various applications. The main focus lies not in achieving greater precision, as conventional architectures have already reached picosecond levels. Instead, the challenge stems from the use of low resources and the substantial expansion in the number of channels. This study presents a novel architecture for the implementation of time-to-digital converters (TDCs) in applications where resources are constrained. The introduced field-programmable-gate-array (FPGA)-based TDC offers a resolution of 415.84 ps, a single-shot precision of 0.45 least significant bits (LSBs) (186 ps r.m.s.) while maintaining a minimal resource occupancy. Built upon a multishift phase counter, the TDC is extended with a tap delay using the input delay available in the FPGA hardware input, doubling the resolution of the TDC. The resource utilization is minimized when compared to low-resource state-of-the-art TDCs. The number of look-up tables (LUTs) has been reduced to 102, and the number of registers to 213. Furthermore, the presented TDC exhibits favorable differential nonlinearity (DNL) (0.2 LSBs) and integral nonlinearity (0.15 LSBs). The TDC has been successfully implemented on an Artix7-2 from Xilinx. This design provides a resource-effective solution for applications requiring high precision and low resource consumption.
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