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Carrio, F. (2022). The Data Acquisition System for the ATLAS Tile Calorimeter Phase-II Upgrade Demonstrator. IEEE Trans. Nucl. Sci., 69(4), 687–695.
Abstract: The tile calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the large hadron collider (LHC). In 2025, the LHC will be upgraded leading to the high luminosity LHC (HL-LHC). The HL-LHC will deliver an instantaneous luminosity up to seven times larger than the LHC nominal luminosity. The ATLAS Phase-II upgrade (2025-2027) will accommodate the subdetectors to the HL-LHC requirements. As part of this upgrade, the majority of the TileCal on-detector and off-detector electronics will be replaced using a new readout strategy, where the on-detector electronics will digitize and transmit digitized detector data to the off-detector electronics at the bunch crossing frequency (40 MHz). In the counting rooms, the off-detector electronics will compute reconstructed trigger objects for the first-level trigger and will store the digitized samples in pipelined buffers until the reception of a trigger acceptance signal. The off-detector electronics will also distribute the LHC clock to the on-detector electronics embedded within the digital data stream. The TileCal Phase-II upgrade project has undertaken an extensive research and development program that includes the development of a Demonstrator module to evaluate the performance of the new clock and readout architecture envisaged for the HL-LHC. The Demonstrator module equipped with the latest version of the on-detector electronics was built and inserted into the ATLAS experiment. The Demonstrator module is operated and read out using a Tile PreProcessor (TilePPr) Demonstrator which enables backward compatibility with the present ATLAS Trigger and Data AcQuisition (TDAQ), and the timing, trigger, and command (TTC) systems. This article describes in detail the main hardware and firmware components of the clock distribution and data acquisition systems for the Demonstrator module, focusing on the TilePPr Demonstrator.
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Real, D., Calvo, D., Manzaneda, M., Diaz, A., Gozzini, S. R., Zornoza, J. D., et al. (2025). Novel Hybrid Low-Resource Field-Programmable-Gate-Array Time-to-Digital-Converter Architecture. IEEE Trans. Instrum. Meas., 74, 2000812–12pp.
Abstract: Time measurements are challenging in electronics given their various applications. The main focus lies not in achieving greater precision, as conventional architectures have already reached picosecond levels. Instead, the challenge stems from the use of low resources and the substantial expansion in the number of channels. This study presents a novel architecture for the implementation of time-to-digital converters (TDCs) in applications where resources are constrained. The introduced field-programmable-gate-array (FPGA)-based TDC offers a resolution of 415.84 ps, a single-shot precision of 0.45 least significant bits (LSBs) (186 ps r.m.s.) while maintaining a minimal resource occupancy. Built upon a multishift phase counter, the TDC is extended with a tap delay using the input delay available in the FPGA hardware input, doubling the resolution of the TDC. The resource utilization is minimized when compared to low-resource state-of-the-art TDCs. The number of look-up tables (LUTs) has been reduced to 102, and the number of registers to 213. Furthermore, the presented TDC exhibits favorable differential nonlinearity (DNL) (0.2 LSBs) and integral nonlinearity (0.15 LSBs). The TDC has been successfully implemented on an Artix7-2 from Xilinx. This design provides a resource-effective solution for applications requiring high precision and low resource consumption.
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