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Records |
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Author |
Aliaga, R.J. |
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Title |
Real-Time Estimation of Zero Crossings of Sampled Signals for Timing Using Cubic Spline Interpolation |
Type |
Journal Article |
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Year |
2017 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
64 |
Issue |
8 |
Pages |
2414-2422 |
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Keywords |
Digital arithmetic; digital circuits; digital timing; field-programmable gate array (FPGA); interpolation; signal processing algorithms; splines time estimation; time resolution |
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Abstract |
A scheme is proposed for hardware estimation of the location of zero crossings of sampled signals with subsample resolution for timing applications, which consists of interpolating the signal with a cubic spline near the zero crossing and then finding the root of the resulting polynomial. An iterative algorithm based on the bisection method is presented that obtains one bit of the result per step and admits an efficient digital implementation using fixed-point representation. In particular, the root estimation iteration involves only two additions, and the initial values can be obtained from finite impulse response (FIR) filters with certain symmetry properties. It is shown that this allows online real-time estimation of timestamps in free-running sampling detector systems with improved accuracy with respect to the more common linear interpolation. The method is evaluated with simulations using ideal and real timing signals, and estimates are given for the resource usage and speed of its implementation. |
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Address |
[Aliaga, Ramon J.] Inst Fis Corpuscular, Paterna 46980, Spain, Email: raalva@upvnet.upv.es |
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Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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0018-9499 |
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Notes |
WOS:000411027700008 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
no |
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Call Number |
IFIC @ pastor @ |
Serial |
3301 |
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Author |
Egea Canet, F.J. et al; Gadea, A.; Huyuk, T. |
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Title |
A New Front-End High-Resolution Sampling Board for the New-Generation Electronics of EXOGAM2 and NEDA Detectors |
Type |
Journal Article |
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Year |
2015 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
62 |
Issue |
3 |
Pages |
1056-1062 |
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Keywords |
Acquisition in HP-Ge detectors; high-speed ADCs; low-noise electronics design |
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Abstract |
This paper presents the final design and results of the FADC Mezzanine for the EXOGAM (EXOtic GAMma array spectrometer) and NEDA (Neutron Detector Array) detectors. The measurements performed include those of studying the effective number of bits, the energy resolution using HP-Ge detectors, as well as timing histograms and discrimination performance. Finally, the conclusion shows how a common digitizing device has been integrated in the experimental environment of two very different detectors which combine both low-noise acquisition and fast sampling rates. Not only the integration fulfilled the expected specifications on both systems, but it also showed how a study of synergy between detectors could lead to the reduction of resources and time by applying a common strategy. |
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Address |
[Egea Canet, F. J.; Gonzalez, V.; Sanchis, E.] Univ Valencia, Dept Elect Engn, Escola Tecn Super Engn, Valencia, Spain, Email: jaegea@ific.uv.es |
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Ieee-Inst Electrical Electronics Engineers Inc |
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0018-9499 |
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Notes |
WOS:000356458000028 |
Approved |
no |
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yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
2278 |
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Permanent link to this record |
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Author |
Egea Canet, F.J. et al; Gadea, A.; Huyuk, T. |
![find record details (via OpenURL) openurl](img/xref.gif)
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Title |
Digital Front-End Electronics for the Neutron Detector NEDA |
Type |
Journal Article |
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Year |
2015 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
62 |
Issue |
3 |
Pages |
1063-1069 |
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Keywords |
Digital systems; front-end electronics; neutron detectors; neutron-gamma discrimination |
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Abstract |
This paper presents the design of the NEDA (Neutron Detector Array) electronics, a first attempt to involve the use of digital electronics in large neutron detector arrays. Starting from the front-end modules attached to the PMTs (PhotoMultiplier Tubes) and ending up with the data processing workstations, a comprehensive electronic system capable of dealing with the acquisition and pre-processing of the neutron array is detailed. Among the electronic modules required, we emphasize the front-end analog processing, the digitalization, digital pre-processing and communications firmware, as well as the integration of the GTS (Global Trigger and Synchronization) system, already used successfully in AGATA (Advanced Gamma Tracking Array). The NEDA array will be available for measurements in 2016. |
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Address |
[Egea Canet, F. J.; Gonzalez, V.; Sanchis, E.] Univ Valencia, Dept Elect Engn, Escola Tecn Super Engn, Valencia, Spain, Email: jaegea@ific.uv.es |
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Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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0018-9499 |
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Notes |
WOS:000356458000029 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
2279 |
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Permanent link to this record |
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Author |
Dimmock, M.R.; Nikulin, D.A.; Gillam, J.E.; Nguyen, C.V. |
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Title |
An OpenCL Implementation of Pinhole Image Reconstruction |
Type |
Journal Article |
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Year |
2012 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
59 |
Issue |
4 |
Pages |
1738-1749 |
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Keywords |
Collimator; GPU; OpenCL; pinhole |
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Abstract |
AC++/OpenCL software platform for emission image reconstruction of data from pinhole cameras has been developed. The software incorporates a new, accurate but computationally costly, probability distribution function for operating on list-mode data from detector stacks. The platform architecture is more general than previous works, supporting advanced models such as arbitrary probability distribution, collimation geometry and detector stack geometry. The software was implemented such that all performance-critical operations occur on OpenCL devices, generally GPUs. The performance of the software is tested on several commodity CPU and GPU devices. |
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[Dimmock, Matthew R.; Nikulin, Dmitri A.; Nguyen, Chuong V.] Monash Univ, Sch Phys, Melbourne, Vic 3800, Australia, Email: matthew.dimmock@synchrotron.org.au; |
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Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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0018-9499 |
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Notes |
WOS:000307893900034 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
1145 |
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Permanent link to this record |
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Author |
Carrio, F.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Higon-Rodriguez, E.; Marin, C.; Moreno, P.; Sanchis, E.; Solans, C.; Valero, A.; Valls Ferrer, J.A. |
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Title |
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment |
Type |
Journal Article |
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Year |
2011 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
58 |
Issue |
4 |
Pages |
1657-1663 |
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Keywords |
High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices |
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Abstract |
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol. |
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Address |
[Carrio, F; Gonzalez, V; Marin, C; Sanchis, E] Univ Valencia, Dept Elect Engn, E-46100 Valencia, Spain, Email: vicente.gonzalez@uv.es |
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Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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ISSN |
0018-9499 |
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Notes |
WOS:000293975700037 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
no |
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Call Number |
IFIC @ elepoucu @ |
Serial |
722 |
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Permanent link to this record |