| |
Records |
Links |
|
Author |
Miñano, M. |
|
| |
Title |
Radiation Hard Silicon Strips Detectors for the SLHC |
Type |
Journal Article |
| |
Year |
2011 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
|
| |
Volume |
58 |
Issue |
3 |
Pages |
1135-1140 |
|
| |
Keywords  |
High energy physics; microstrip; radiation detectors; silicon; SLHC |
|
| |
Abstract |
While the Large Hadron Collider (LHC) began taking data in 2009, scenarios for a machine upgrade to achieve a much higher luminosity are being developed. In the current planning, it is foreseen to increase the luminosity of the LHC at CERN around 2018. As radiation damage scales with integrated luminosity, the particle physics experiments will need to be equipped with a new generation of radiation hard detectors. This article reports on the status of the R&D projects on radiation hard silicon strips detectors for particle physics, linked to the Large Hadron Collider Upgrade, super-LHC (sLHC) of the ATLAS microstrip detector. The primary focus of this report is on measuring the radiation hardness of the silicon materials and the detectors under study. This involves designing silicon detectors, irradiating them to the sLHC radiation levels and studying their performance as particle detectors. The most promising silicon detector for the different radiation levels in the different regions of the ATLAS microstrip detector will be presented. Important challenges related to engineering layout, powering, cooling and reading out a very large strip detector are presented. Ideas on possible schemes for the layout and support mechanics will be shown. |
|
| |
Address |
IFIC UV CSIC, Inst Fis Corpuscular, E-46071 Valencia, Spain, Email: mercedes.minano@ific.uv.es |
|
| |
Corporate Author |
|
Thesis |
|
|
| |
Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
|
Editor |
|
|
| |
Language |
English |
Summary Language |
|
Original Title |
|
|
| |
Series Editor |
|
Series Title |
|
Abbreviated Series Title |
|
|
| |
Series Volume |
|
Series Issue |
|
Edition |
|
|
| |
ISSN |
0018-9499 |
ISBN |
|
Medium |
|
|
| |
Area |
|
Expedition |
|
Conference |
|
|
| |
Notes |
ISI:000291659300001 |
Approved |
no |
|
| |
Is ISI |
yes |
International Collaboration |
no |
|
| |
Call Number |
IFIC @ pastor @ |
Serial |
651 |
|
| Permanent link to this record |
| |
|
| |
|
Author |
Carrio, F.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Higon-Rodriguez, E.; Marin, C.; Moreno, P.; Sanchis, E.; Solans, C.; Valero, A.; Valls Ferrer, J.A. |
|
| |
Title |
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment |
Type |
Journal Article |
| |
Year |
2011 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
|
| |
Volume |
58 |
Issue |
4 |
Pages |
1657-1663 |
|
| |
Keywords |
High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices |
|
| |
Abstract |
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol. |
|
| |
Address |
[Carrio, F; Gonzalez, V; Marin, C; Sanchis, E] Univ Valencia, Dept Elect Engn, E-46100 Valencia, Spain, Email: vicente.gonzalez@uv.es |
|
| |
Corporate Author |
|
Thesis |
|
|
| |
Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
|
Editor |
|
|
| |
Language |
English |
Summary Language |
|
Original Title |
|
|
| |
Series Editor |
|
Series Title |
|
Abbreviated Series Title |
|
|
| |
Series Volume |
|
Series Issue |
|
Edition |
|
|
| |
ISSN |
0018-9499 |
ISBN |
|
Medium |
|
|
| |
Area |
|
Expedition |
|
Conference |
|
|
| |
Notes |
WOS:000293975700037 |
Approved |
no |
|
| |
Is ISI |
yes |
International Collaboration |
no |
|
| |
Call Number |
IFIC @ elepoucu @ |
Serial |
722 |
|
| Permanent link to this record |
| |
|
| |
|
Author |
Barrientos, D.; Bellato, M.; Bazzacco, D.; Bortolato, D.; Cocconi, P.; Gadea, A.; Gonzalez, V.; Gulmini, M.; Isocrate, R.; Mengoni, D.; Pullia, A.; Recchia, F.; Rosso, D.; Sanchis, E.; Toniolo, N.; Ur, C.A.; Valiente-Dobon, J.J. |
|
| |
Title |
Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array |
Type |
Journal Article |
| |
Year |
2015 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
|
| |
Volume |
62 |
Issue |
6 |
Pages |
3134-3139 |
|
| |
Keywords |
FPGA; front-end electronics; gamma-ray spectroscopy; germanium detectors |
|
| |
Abstract |
In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.53% at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs. |
|
| |
Address |
[Barrientos, D.; Bortolato, D.; Cocconi, P.; Gulmini, M.; Rosso, D.; Toniolo, N.; Valiente-Dobon, J. J.] Ist Nazl Fis Nucl, Lab Nazl Legnaro, I-35020 Padua, Italy, Email: diego.barrientos@lnl.infn.it |
|
| |
Corporate Author |
|
Thesis |
|
|
| |
Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
|
Editor |
|
|
| |
Language |
English |
Summary Language |
|
Original Title |
|
|
| |
Series Editor |
|
Series Title |
|
Abbreviated Series Title |
|
|
| |
Series Volume |
|
Series Issue |
|
Edition |
|
|
| |
ISSN |
0018-9499 |
ISBN |
|
Medium |
|
|
| |
Area |
|
Expedition |
|
Conference |
|
|
| |
Notes |
WOS:000372013500005 |
Approved |
no |
|
| |
Is ISI |
yes |
International Collaboration |
yes |
|
| |
Call Number |
IFIC @ pastor @ |
Serial |
2612 |
|
| Permanent link to this record |
| |
|
| |
|
Author |
Egea Canet, F.J. et al; Gadea, A.; Huyuk, T. |
|
| |
Title |
Digital Front-End Electronics for the Neutron Detector NEDA |
Type |
Journal Article |
| |
Year |
2015 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
|
| |
Volume |
62 |
Issue |
3 |
Pages |
1063-1069 |
|
| |
Keywords |
Digital systems; front-end electronics; neutron detectors; neutron-gamma discrimination |
|
| |
Abstract |
This paper presents the design of the NEDA (Neutron Detector Array) electronics, a first attempt to involve the use of digital electronics in large neutron detector arrays. Starting from the front-end modules attached to the PMTs (PhotoMultiplier Tubes) and ending up with the data processing workstations, a comprehensive electronic system capable of dealing with the acquisition and pre-processing of the neutron array is detailed. Among the electronic modules required, we emphasize the front-end analog processing, the digitalization, digital pre-processing and communications firmware, as well as the integration of the GTS (Global Trigger and Synchronization) system, already used successfully in AGATA (Advanced Gamma Tracking Array). The NEDA array will be available for measurements in 2016. |
|
| |
Address |
[Egea Canet, F. J.; Gonzalez, V.; Sanchis, E.] Univ Valencia, Dept Elect Engn, Escola Tecn Super Engn, Valencia, Spain, Email: jaegea@ific.uv.es |
|
| |
Corporate Author |
|
Thesis |
|
|
| |
Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
|
Editor |
|
|
| |
Language |
English |
Summary Language |
|
Original Title |
|
|
| |
Series Editor |
|
Series Title |
|
Abbreviated Series Title |
|
|
| |
Series Volume |
|
Series Issue |
|
Edition |
|
|
| |
ISSN |
0018-9499 |
ISBN |
|
Medium |
|
|
| |
Area |
|
Expedition |
|
Conference |
|
|
| |
Notes |
WOS:000356458000029 |
Approved |
no |
|
| |
Is ISI |
yes |
International Collaboration |
yes |
|
| |
Call Number |
IFIC @ pastor @ |
Serial |
2279 |
|
| Permanent link to this record |
| |
|
| |
|
Author |
Aliaga, R.J. |
|
| |
Title |
Real-Time Estimation of Zero Crossings of Sampled Signals for Timing Using Cubic Spline Interpolation |
Type |
Journal Article |
| |
Year |
2017 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
|
| |
Volume |
64 |
Issue |
8 |
Pages |
2414-2422 |
|
| |
Keywords |
Digital arithmetic; digital circuits; digital timing; field-programmable gate array (FPGA); interpolation; signal processing algorithms; splines time estimation; time resolution |
|
| |
Abstract |
A scheme is proposed for hardware estimation of the location of zero crossings of sampled signals with subsample resolution for timing applications, which consists of interpolating the signal with a cubic spline near the zero crossing and then finding the root of the resulting polynomial. An iterative algorithm based on the bisection method is presented that obtains one bit of the result per step and admits an efficient digital implementation using fixed-point representation. In particular, the root estimation iteration involves only two additions, and the initial values can be obtained from finite impulse response (FIR) filters with certain symmetry properties. It is shown that this allows online real-time estimation of timestamps in free-running sampling detector systems with improved accuracy with respect to the more common linear interpolation. The method is evaluated with simulations using ideal and real timing signals, and estimates are given for the resource usage and speed of its implementation. |
|
| |
Address |
[Aliaga, Ramon J.] Inst Fis Corpuscular, Paterna 46980, Spain, Email: raalva@upvnet.upv.es |
|
| |
Corporate Author |
|
Thesis |
|
|
| |
Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
|
Editor |
|
|
| |
Language |
English |
Summary Language |
|
Original Title |
|
|
| |
Series Editor |
|
Series Title |
|
Abbreviated Series Title |
|
|
| |
Series Volume |
|
Series Issue |
|
Edition |
|
|
| |
ISSN |
0018-9499 |
ISBN |
|
Medium |
|
|
| |
Area |
|
Expedition |
|
Conference |
|
|
| |
Notes |
WOS:000411027700008 |
Approved |
no |
|
| |
Is ISI |
yes |
International Collaboration |
no |
|
| |
Call Number |
IFIC @ pastor @ |
Serial |
3301 |
|
| Permanent link to this record |
