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Author Esteve, R.; Toledo, J.F.; Herrero, V.; Simon, A.; Monrabal, F.; Alvarez, V.; Rodriguez, J.; Querol, M.; Ballester, F.
Title The Event Detection System in the NEXT-White Detector Type Journal Article
Year 2021 Publication Sensors Abbreviated Journal Sensors
Volume 21 Issue 2 Pages 673 - 18pp
Keywords xenon TPC; trigger concepts; data acquisition circuits; FPGA
Abstract This article describes the event detection system of the NEXT-White detector, a 5 kg high pressure xenon TPC with electroluminescent amplification, located in the Laboratorio Subterraneo de Canfranc (LSC), Spain. The detector is based on a plane of photomultipliers (PMTs) for energy measurements and a silicon photomultiplier (SiPM) tracking plane for offline topological event filtering. The event detection system, based on the SRS-ATCA data acquisition system developed in the framework of the CERN RD51 collaboration, has been designed to detect multiple events based on online PMT signal energy measurements and a coincidence-detection algorithm. Implemented on FPGA, the system has been successfully running and evolving during NEXT-White operation. The event detection system brings some relevant and new functionalities in the field. A distributed double event processor has been implemented to detect simultaneously two different types of events thus allowing simultaneous calibration and physics runs. This special feature provides constant monitoring of the detector conditions, being especially relevant to the lifetime and geometrical map computations which are needed to correct high-energy physics events. Other features, like primary scintillation event rejection, or a double buffer associated with the type of event being searched, help reduce the unnecessary data throughput thus minimizing dead time and improving trigger efficiency.
Address [Esteve Bosch, Raul; Toledo Alarcon, Jose F.; Herrero Bosch, Vicente; Alvarez Puerta, Vicente; Rodriguez Samaniego, Javier; Ballester Merelo, Francisco] Univ Politecn Valencia, CSIC, Inst Instrumentac Imagen Mol I3M, Ctr Mixto, Camino Vera S-N, Valencia 46022, Spain, Email: rauesbos@eln.upv.es;
Corporate Author Thesis
Publisher Mdpi Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) ISBN Medium
Area Expedition Conference
Notes WOS:000611719600001 Approved no
Is ISI yes International Collaboration yes
Call Number IFIC @ pastor @ Serial 4693
Permanent link to this record
 
 
Author KM3NeT Collaboration (Aiello, S. et al); Calvo, D.; Coleiro, A.; Colomer, M.; Gozzini, S.R.; Hernandez-Rey, J.J.; Illuminati, G.; Khan Chowdhury, N.R.; Manczak, J.; Pieterse, C.; Real, D.; Thakore, T.; Zornoza, J.D.; Zuñiga, J.
Title The Control Unit of the KM3NeT Data Acquisition System Type Journal Article
Year 2020 Publication Computer Physics Communications Abbreviated Journal Comput. Phys. Commun.
Volume 256 Issue Pages 107433 - 16pp
Keywords KM3NeT; Data acquisition control; Neutrino detector; Astroparticle detector; 07.05.Hd; 29.85.Ca
Abstract The KM3NeT Collaboration runs a multi-site neutrino observatory in the Mediterranean Sea. Water Cherenkov particle detectors, deep in the sea and far off the coasts of France and Italy, are already taking data while incremental construction progresses. Data Acquisition Control software is operating off-shore detectors as well as testing and qualification stations for their components. The software, named Control Unit, is highly modular. It can undergo upgrades and reconfiguration with the acquisition running. Interplay with the central database of the Collaboration is obtained in a way that allows for data taking even if Internet links fail. In order to simplify the management of computing resources in the long term, and to cope with possible hardware failures of one or more computers, the KM3NeT Control Unit software features a custom dynamic resource provisioning and failover technology, which is especially important for ensuring continuity in case of rare transient events in multi-messenger astronomy. The software architecture relies on ubiquitous tools and broadly adopted technologies and has been successfully tested on several operating systems.
Address [Aiello, S.; Leonora, E.; Longhitano, F.; Randazzo, N.] Ist Nazl Fis Nucl, Sez Catania, Via Santa Sofia 64, I-95123 Catania, Italy, Email: cbozza@unisa.it;
Corporate Author Thesis
Publisher Elsevier Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) 0010-4655 ISBN Medium
Area Expedition Conference
Notes WOS:000590251400011 Approved no
Is ISI yes International Collaboration yes
Call Number IFIC @ pastor @ Serial 4616
Permanent link to this record
 
 
Author Carrio, F.
Title The Data Acquisition System for the ATLAS Tile Calorimeter Phase-II Upgrade Demonstrator Type Journal Article
Year 2022 Publication IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.
Volume 69 Issue 4 Pages 687-695
Keywords Large Hadron Collider; Data acquisition; Field programmable gate arrays; Clocks; Detectors; Computer architecture; Microprocessors; ATLAS tile calorimeter (TileCal); data acquisition (DAQ) systems; field-programmable gate array (FPGA); high energy physics; high-speed electronics
Abstract The tile calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the large hadron collider (LHC). In 2025, the LHC will be upgraded leading to the high luminosity LHC (HL-LHC). The HL-LHC will deliver an instantaneous luminosity up to seven times larger than the LHC nominal luminosity. The ATLAS Phase-II upgrade (2025-2027) will accommodate the subdetectors to the HL-LHC requirements. As part of this upgrade, the majority of the TileCal on-detector and off-detector electronics will be replaced using a new readout strategy, where the on-detector electronics will digitize and transmit digitized detector data to the off-detector electronics at the bunch crossing frequency (40 MHz). In the counting rooms, the off-detector electronics will compute reconstructed trigger objects for the first-level trigger and will store the digitized samples in pipelined buffers until the reception of a trigger acceptance signal. The off-detector electronics will also distribute the LHC clock to the on-detector electronics embedded within the digital data stream. The TileCal Phase-II upgrade project has undertaken an extensive research and development program that includes the development of a Demonstrator module to evaluate the performance of the new clock and readout architecture envisaged for the HL-LHC. The Demonstrator module equipped with the latest version of the on-detector electronics was built and inserted into the ATLAS experiment. The Demonstrator module is operated and read out using a Tile PreProcessor (TilePPr) Demonstrator which enables backward compatibility with the present ATLAS Trigger and Data AcQuisition (TDAQ), and the timing, trigger, and command (TTC) systems. This article describes in detail the main hardware and firmware components of the clock distribution and data acquisition systems for the Demonstrator module, focusing on the TilePPr Demonstrator.
Address [Carrio, F.] Inst Fis Corpuscular CSIC UV, Paterna 46980, Spain, Email: fernando.carrio@cern.ch
Corporate Author Thesis
Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) 0018-9499 ISBN Medium
Area Expedition Conference
Notes WOS:000803113800016 Approved no
Is ISI yes International Collaboration no
Call Number IFIC @ pastor @ Serial 5244
Permanent link to this record
 
 
Author Valero, A.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Hernandez Jimenez, Y.; Higon-Rodriguez, E.; Sanchis, E.; Solans, C.; Torres, J.; Valls Ferrer, J.A.
Title The ATLAS tile calorimeter ROD injector and multiplexer board Type Journal Article
Year 2011 Publication Nuclear Instruments & Methods in Physics Research A Abbreviated Journal Nucl. Instrum. Methods Phys. Res. A
Volume 629 Issue 1 Pages 74-79
Keywords LHC; ATLAS; Calorimeter; Data acquisition; FPGA; Bit error rate
Abstract The ATLAS Tile Calorimeter is a sampling detector composed by cells made of iron-scintillator tiles. The calorimeter cell signals are digitized in the front-end electronics and transmitted to the Read-Out Drivers (RODs) at the first level trigger rate. The ROD receives triggered data from up to 9856 channels and provides the energy, phase and quality factor of the signals to the second level trigger. The back-end electronics is divided into four partitions containing eight RODs each. Therefore, a total of 32 RODs are used to process and transmit the data of the TileCal detector. In order to emulate the detector signals in the production and commissioning of ROD modules a board called ROD Injector and Multiplexer Board (RIMBO) was designed. In this paper, the RIMBO main functional blocks, PCB design and the different operation modes are described. It is described the crucial role of the board within the TileCal ROD test-bench in order to emulate the front-end electronics during the validation of ROD boards as well as during the evaluation of the ROD signal reconstruction algorithms. Finally, qualification and performance results for the injection operation mode obtained during the Tile Calorimeter ROD production tests are presented.
Address [Valero, A.; Castillo, V.; Ferrer, A.; Hernandez, Y.; Higon, E.; Solans, C.; Valls, J. A.] Univ Valencia, CSIC, Inst Fis Corpuscular, Valencia 46071, Spain, Email: alberto.valero@cern.ch
Corporate Author Thesis
Publisher Elsevier Science Bv Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) 0168-9002 ISBN Medium
Area Expedition Conference
Notes ISI:000287556100012 Approved no
Is ISI yes International Collaboration no
Call Number IFIC @ pastor @ Serial 555
Permanent link to this record
 
 
Author Aliaga, R.J.; Herrero-Bosch, V.; Capra, S.; Pullia, A.; Duenas, J.A.; Grassi, L.; Triossi, A.; Domingo-Pardo, C.; Gadea, R.; Gonzalez, V.; Huyuk, T.; Sanchis, E.; Gadea, A.; Mengoni, D.
Title Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC Type Journal Article
Year 2015 Publication Nuclear Instruments & Methods in Physics Research A Abbreviated Journal Nucl. Instrum. Methods Phys. Res. A
Volume 800 Issue Pages 34-39
Keywords Analog memory; Dead time; Detector readout; Front-end electronics; Switched Capacitor Array (SCA); Triggerless data acquisition
Abstract The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling, Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.
Address [Aliaga, R. J.; Domingo-Pardo, C.; Hueyuek, T.; Gadea, A.] Inst Fis Corpuscular, Paterna 46980, Spain, Email: raalva@ific.uv.es
Corporate Author Thesis
Publisher Elsevier Science Bv Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) 0168-9002 ISBN Medium
Area Expedition Conference
Notes WOS:000361878200006 Approved no
Is ISI yes International Collaboration yes
Call Number IFIC @ pastor @ Serial 2407
Permanent link to this record
 
 
Author Agramunt, J. et al; Tain, J.L.; Albiol, F.; Algora, A.; Domingo-Pardo, C.; Jordan, M. D.; Rubio, B.; Tarifeño-Saldivia, A.; Valencia, E.
Title Characterization of a neutron-beta counting system with beta-delayed neutron emitters Type Journal Article
Year 2016 Publication Nuclear Instruments & Methods in Physics Research A Abbreviated Journal Nucl. Instrum. Methods Phys. Res. A
Volume 807 Issue Pages 69-78
Keywords Beta-delayed neutron emission probability; Neutron and beta counters; Self-triggered digital data acquisition system; Geant4 simulations
Abstract A new detection system for the measurement of beta-delayed neutron emission probabilities has been characterized using fission products with well known beta-delayed neutron emission properties. The setup consists of BELEN-20, a 4 pi-neutron counter with twenty He-3 proportional tubes arranged inside a large polyethylene neutron moderator, a thin Si detector for beta counting and a self-triggering digital data acquisition system. The use of delayed-neutron precursors with different neutron emission windows allowed the study of the effect of energy dependency on neutron, beta and beta-neutron rates. The observed effect is well reproduced by Monte Carlo simulations. The impact of this dependency on the accuracy of neutron emission probabilities is discussed. A new accurate value of the neutron emission probability for the important delayed-neutron precursor I-137 was obtained, P-n = 7.76(14)%.
Address [Agramunt, J.; Tain, J. L.; Albiol, E.; Algora, A.; Domingo-Pardo, C.; Jordan, M. D.; Rubio, B.; Tarifeno-Saldivia, A.; Valencia, E.] Univ Valencia, CSIC, Inst Fis Corpuscular, E-46071 Valencia, Spain, Email: Tain@ific.uv.es
Corporate Author Thesis
Publisher Elsevier Science Bv Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) 0168-9002 ISBN Medium
Area Expedition Conference
Notes WOS:000365596200010 Approved no
Is ISI yes International Collaboration yes
Call Number IFIC @ pastor @ Serial 2481
Permanent link to this record
 
 
Author Hueso-Gonzalez, F.; Casaña Copado, J.V.; Fernandez Prieto, A.; Gallas Torreira, A.; Lemos Cid, E.; Ros Garcia, A.; Vazquez Regueiro, P.; Llosa, G.
Title A dead-time-free data acquisition system for prompt gamma-ray measurements during proton therapy treatments Type Journal Article
Year 2022 Publication Nuclear Instruments & Methods in Physics Research A Abbreviated Journal Nucl. Instrum. Methods Phys. Res. A
Volume 1033 Issue Pages 166701 - 9pp
Keywords Data acquisition; Dead time; Pile-up; Digital signal processing
Abstract In cancer patients undergoing proton therapy, a very intense secondary radiation is produced during the treatment, which lasts around one minute. About one billion prompt gamma-rays are emitted per second, and their detection with fast scintillation detectors is useful for monitoring a correct beam delivery. To cope with the expected count rate and pile-up, as well as the scarce statistics due to the short treatment duration, we developed an eidetic data acquisition system capable of continuously digitizing the detector signal with a high sampling rate and without any dead time. By streaming the fully unprocessed waveforms to the computer, complex pile-up decomposition algorithms can be applied and optimized offline. We describe the data acquisition architecture and the multiple experimental tests designed to verify the sustained data throughput speed and the absence of dead time. While the system is tailored for the proton therapy environment, the methodology can be deployed in any other field requiring the recording of raw waveforms at high sampling rates with zero dead time.
Address
Corporate Author Thesis
Publisher Elsevier Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) 0168-9002 ISBN Medium
Area Expedition Conference
Notes WOS:000794040600002 Approved no
Is ISI yes International Collaboration no
Call Number IFIC @ pastor @ Serial 5318
Permanent link to this record
 
 
Author Marco-Hernandez, R.
Title Development of a beam test telescope based on the Alibava readout system Type Journal Article
Year 2011 Publication Journal of Instrumentation Abbreviated Journal J. Instrum.
Volume 6 Issue Pages C01002 - 7pp
Keywords Particle tracking detectors; Data acquisition circuits; Front-end electronics for detector readout; Digital electronic circuits
Abstract A telescope for a beam test have been developed as a result of a collaboration among the University of Liverpool, Centro Nacional de Microelectronica (CNM) of Barcelona and Instituto de Fisica Corpuscular (IFIC) of Valencia. This system is intended to carry out both analogue charge collection and spatial resolution measurements with different types of microstrip or pixel silicon detectors in a beam test environment. The telescope has four XY measurement as well as trigger planes (XYT board) and it can accommodate up to twelve devices under test (DUT board). The DUT board uses two Beetle ASICs for the readout of chilled silicon detectors. The board could operate in a self-triggering mode. The board features a temperature sensor and it can be mounted on a rotary stage. A peltier element is used for cooling the DUT. Each XYT board measures the track space points using two silicon strip detectors connected to two Beetle ASICs. It can also trigger on the particle tracks in the beam test. The board includes a CPLD which allows for the synchronization of the trigger signal to a common clock frequency, delaying and implementing coincidence with other XYT boards. An Alibava mother board is used to read out and to control each XYT/DUT board from a common trigger signal and a common clock signal. The Alibava board has a TDC on board to have a time stamp of each trigger. The data collected by each Alibava board is sent to a master card by means of a local data/address bus following a custom digital protocol. The master board distributes the trigger, clock and reset signals. It also merges the data streams from up to sixteen Alibava boards. The board has also a test channel for testing in a standard mode a XYT or DUT board. This board is implemented with a Xilinx development board and a custom patch board. The master board is connected with the DAQ software via 100M Ethernet. Track based alignment software has also been developed for the data obtained with the DAQ software.
Address [Marco-Hernandez, R.; Alibava Collaboration] CSIC UV, Inst Fis Corpuscular, E-46980 Paterna, Valencia, Spain, Email: rmarco@ific.uv.es
Corporate Author Thesis
Publisher Iop Publishing Ltd Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) 1748-0221 ISBN Medium
Area Expedition Conference
Notes ISI:000291345600007 Approved no
Is ISI yes International Collaboration no
Call Number IFIC @ elepoucu @ Serial 644
Permanent link to this record
 
 
Author Esteve, R.; Toledo, J.; Monrabal, F.; Lorca, D.; Serra, L.; Mari, A.; Gomez-Cadenas, J.J.; Liubarsky, I.; Mora, F.
Title The trigger system in the NEXT-DEMO detector Type Journal Article
Year 2012 Publication Journal of Instrumentation Abbreviated Journal J. Instrum.
Volume 7 Issue Pages C12001 - 9pp
Keywords Data acquisition circuits; Trigger algorithms; Trigger concepts and systems (hardware and software); Modular electronics
Abstract NEXT-DEMO is a prototype of NEXT (Neutrino Experiment with Xenon TPC), an experiment to search for neutrino-less double beta decay using a 100 kg radio-pure, 90 % enriched (136Xe isotope) high-pressure gaseous xenon TPC with electroluminescence readout. The detector is based on a PMT plane for energy measurements and a SiPM tracking plane for topological event filtering. The experiment will be located in the Canfranc Underground Laboratory in Spain. Front-end electronics, trigger and data-acquisition systems (DAQ) have been built. The DAQ is an implementation of the Scalable Readout System (RD51 collaboration) based on FPGA. Our approach for trigger is to have a distributed and reconfigurable system in the DAQ itself. Moreover, the trigger allows on-line triggering based on the detection of primary or secondary scintillation light, or a combination of both, that arrives to the PMT plane.
Address [Esteve, R.; Toledo, J.; Mari, A.; Mora, F.] Univ Politecn Valencia, Inst Instrumentac Imagen Mol I3M, Valencia 46022, Spain, Email: rauesbos@eln.upv.es
Corporate Author Thesis
Publisher Iop Publishing Ltd Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) 1748-0221 ISBN Medium
Area Expedition Conference
Notes WOS:000312962500001 Approved no
Is ISI yes International Collaboration no
Call Number IFIC @ pastor @ Serial 1288
Permanent link to this record
 
 
Author Carrio, F.; Kim, H.Y.; Moreno, P.; Reed, R.; Sandrock, C.; Schettino, V.; Shalyugin, A.; Solans, C.; Souza, J.; Usai, G.; Valero, A.
Title Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench Type Journal Article
Year 2014 Publication Journal of Instrumentation Abbreviated Journal J. Instrum.
Volume 9 Issue Pages C03023 - 12pp
Keywords Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms; databases); Data acquisition concepts; Digital electronic circuits
Abstract The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception.
Address [Carrio, F.; Valero, A.] Univ Valencia, CSIC, Inst Fis Corpuscular, E-46980 Paterna, Spain, Email: fernando.carrio@cern.ch
Corporate Author Thesis
Publisher Iop Publishing Ltd Place of Publication Editor
Language English Summary Language Original Title
Series Editor Series Title Abbreviated Series Title
Series Volume Series Issue Edition
ISSN (up) 1748-0221 ISBN Medium
Area Expedition Conference
Notes WOS:000336123200023 Approved no
Is ISI yes International Collaboration yes
Call Number IFIC @ pastor @ Serial 1801
Permanent link to this record