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Miñano, M. (2011). Radiation Hard Silicon Strips Detectors for the SLHC. IEEE Trans. Nucl. Sci., 58(3), 1135–1140.
Abstract: While the Large Hadron Collider (LHC) began taking data in 2009, scenarios for a machine upgrade to achieve a much higher luminosity are being developed. In the current planning, it is foreseen to increase the luminosity of the LHC at CERN around 2018. As radiation damage scales with integrated luminosity, the particle physics experiments will need to be equipped with a new generation of radiation hard detectors. This article reports on the status of the R&D projects on radiation hard silicon strips detectors for particle physics, linked to the Large Hadron Collider Upgrade, super-LHC (sLHC) of the ATLAS microstrip detector. The primary focus of this report is on measuring the radiation hardness of the silicon materials and the detectors under study. This involves designing silicon detectors, irradiating them to the sLHC radiation levels and studying their performance as particle detectors. The most promising silicon detector for the different radiation levels in the different regions of the ATLAS microstrip detector will be presented. Important challenges related to engineering layout, powering, cooling and reading out a very large strip detector are presented. Ideas on possible schemes for the layout and support mechanics will be shown.
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Carrio, F., Castillo Gimenez, V., Ferrer, A., Gonzalez, V., Higon-Rodriguez, E., Marin, C., et al. (2011). Optical Link Card Design for the Phase II Upgrade of TileCal Experiment. IEEE Trans. Nucl. Sci., 58(4), 1657–1663.
Abstract: This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol.
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Yepes, H. (2012). The ANTARES neutrino detector instrumentation. J. Instrum., 7, C01022–9pp.
Abstract: ANTARES is actually the fully operational and the largest neutrino telescope in the Northern hemisphere. Located in the Mediterranean Sea, it consists of a 3D array of 885 photomultiplier tubes (PMTs) arranged in 12 detection lines (25 storeys each), able to detect the Cherenkov light induced by upgoing relativistic muons produced in the interaction of high energy cosmic neutrinos with the detector surroundings. Among its physics goals, the search for neutrino astrophysical sources and the indirect detection of dark matter particles coming from the sun are of particular interest. To reach these goals, good accuracy in track reconstruction is mandatory, so several calibration systems for timing and positioning have been developed. In this contribution we will present the design of the detector, calibration systems, associated equipment and its performance on track reconstruction.
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Carrio, F. (2022). The Data Acquisition System for the ATLAS Tile Calorimeter Phase-II Upgrade Demonstrator. IEEE Trans. Nucl. Sci., 69(4), 687–695.
Abstract: The tile calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the large hadron collider (LHC). In 2025, the LHC will be upgraded leading to the high luminosity LHC (HL-LHC). The HL-LHC will deliver an instantaneous luminosity up to seven times larger than the LHC nominal luminosity. The ATLAS Phase-II upgrade (2025-2027) will accommodate the subdetectors to the HL-LHC requirements. As part of this upgrade, the majority of the TileCal on-detector and off-detector electronics will be replaced using a new readout strategy, where the on-detector electronics will digitize and transmit digitized detector data to the off-detector electronics at the bunch crossing frequency (40 MHz). In the counting rooms, the off-detector electronics will compute reconstructed trigger objects for the first-level trigger and will store the digitized samples in pipelined buffers until the reception of a trigger acceptance signal. The off-detector electronics will also distribute the LHC clock to the on-detector electronics embedded within the digital data stream. The TileCal Phase-II upgrade project has undertaken an extensive research and development program that includes the development of a Demonstrator module to evaluate the performance of the new clock and readout architecture envisaged for the HL-LHC. The Demonstrator module equipped with the latest version of the on-detector electronics was built and inserted into the ATLAS experiment. The Demonstrator module is operated and read out using a Tile PreProcessor (TilePPr) Demonstrator which enables backward compatibility with the present ATLAS Trigger and Data AcQuisition (TDAQ), and the timing, trigger, and command (TTC) systems. This article describes in detail the main hardware and firmware components of the clock distribution and data acquisition systems for the Demonstrator module, focusing on the TilePPr Demonstrator.
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