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Author (down) Carrio, F. doi  openurl
  Title The Data Acquisition System for the ATLAS Tile Calorimeter Phase-II Upgrade Demonstrator Type Journal Article
  Year 2022 Publication IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 69 Issue 4 Pages 687-695  
  Keywords Large Hadron Collider; Data acquisition; Field programmable gate arrays; Clocks; Detectors; Computer architecture; Microprocessors; ATLAS tile calorimeter (TileCal); data acquisition (DAQ) systems; field-programmable gate array (FPGA); high energy physics; high-speed electronics  
  Abstract The tile calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the large hadron collider (LHC). In 2025, the LHC will be upgraded leading to the high luminosity LHC (HL-LHC). The HL-LHC will deliver an instantaneous luminosity up to seven times larger than the LHC nominal luminosity. The ATLAS Phase-II upgrade (2025-2027) will accommodate the subdetectors to the HL-LHC requirements. As part of this upgrade, the majority of the TileCal on-detector and off-detector electronics will be replaced using a new readout strategy, where the on-detector electronics will digitize and transmit digitized detector data to the off-detector electronics at the bunch crossing frequency (40 MHz). In the counting rooms, the off-detector electronics will compute reconstructed trigger objects for the first-level trigger and will store the digitized samples in pipelined buffers until the reception of a trigger acceptance signal. The off-detector electronics will also distribute the LHC clock to the on-detector electronics embedded within the digital data stream. The TileCal Phase-II upgrade project has undertaken an extensive research and development program that includes the development of a Demonstrator module to evaluate the performance of the new clock and readout architecture envisaged for the HL-LHC. The Demonstrator module equipped with the latest version of the on-detector electronics was built and inserted into the ATLAS experiment. The Demonstrator module is operated and read out using a Tile PreProcessor (TilePPr) Demonstrator which enables backward compatibility with the present ATLAS Trigger and Data AcQuisition (TDAQ), and the timing, trigger, and command (TTC) systems. This article describes in detail the main hardware and firmware components of the clock distribution and data acquisition systems for the Demonstrator module, focusing on the TilePPr Demonstrator.  
  Address [Carrio, F.] Inst Fis Corpuscular CSIC UV, Paterna 46980, Spain, Email: fernando.carrio@cern.ch  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000803113800016 Approved no  
  Is ISI yes International Collaboration no  
  Call Number IFIC @ pastor @ Serial 5244  
Permanent link to this record
 

 
Author (down) Belver, D.; Cabanelas, P.; Castro, E.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. doi  openurl
  Title Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall Type Journal Article
  Year 2010 Publication IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 57 Issue 5 Pages 2848-2856  
  Keywords Charge to width algorithm; fast amplifying and digitizing electronics; front-end electronics; HADES; time of flight; timing RPC  
  Abstract A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m(2) divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel Daughter BOard(DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade [1]. The commissioning of the whole RPC wall is finished and the 6 sectors are already mounted in their final position in the HADES spectrometer and ready to take data during the beam-times foreseen for 2010.  
  Address [Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.] Univ Santiago Compostela, LabCAF, Santiago De Compostela 15782, Spain, Email: daniel.belver@usc.es  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes ISI:000283440400007 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ elepoucu @ Serial 349  
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Author (down) Barrio, J.; Etxebeste, A.; Lacasta, C.; Muñoz, E.; Oliver, J.F.; Solaz, C.; Llosa, G. doi  openurl
  Title Performance of VATA64HDR16 ASIC for medical physics applications based on continuous crystals and SiPMs Type Journal Article
  Year 2015 Publication Journal of Instrumentation Abbreviated Journal J. Instrum.  
  Volume 10 Issue Pages P12001 - 12pp  
  Keywords Solid state detectors; Photon detectors for UV, visible and IR photons (solid-state) (PIN diodes, APDs, Si-PMTs, G-APDs, CCDs, EBCCDs, EMCCDs etc); Front-end electronics for detector readout; Gamma detectors (scintillators, CZT, HPG, HgI etc)  
  Abstract Detectors based on Silicon Photomultipliers (SiPMs) coupled to continuous crystals are being tested in medical physics applications due to their potential high resolution and sensitivity. To cope with the high granularity required for a very good spatial resolution, SiPM matrices with a large amount of elements are needed. To be able to read the information coming from each individual channel, dedicated ASICs are employed. The VATA64HDR16 ASIC is a 64-channel, charge-sensitive amplifier that converts the collected charge into a proportional current or voltage signal. A complete assessment of the suitability of that ASIC for medical physics applications based on continuous crystals and SiPMs has been carried out. The input charge range is linear from 20 pC up to 55 pC. The energy resolution obtained at 511 keV is 10% FWHM with a LaBr3 crystal and 16% FWHM with a LYSO crystal. A coincidence timing resolution of 24 ns FWHM is obtained with two LYSO crystals.  
  Address [Barrio, J.; Etxebeste, A.; Lacasta, C.; Munoz, E.; Oliver, J. F.; Solaz, C.; Llosa, G.] Univ Valencia, CSIC, Inst Fis Corpuscular, Parque Cient,C Catedrat Jose Beltran 2, E-46980 Paterna, Spain, Email: John.Barrio@ific.uv.es  
  Corporate Author Thesis  
  Publisher Iop Publishing Ltd Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 1748-0221 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000369998500034 Approved no  
  Is ISI yes International Collaboration no  
  Call Number IFIC @ pastor @ Serial 2548  
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Author (down) Barrientos, D.; Bellato, M.; Bazzacco, D.; Bortolato, D.; Cocconi, P.; Gadea, A.; Gonzalez, V.; Gulmini, M.; Isocrate, R.; Mengoni, D.; Pullia, A.; Recchia, F.; Rosso, D.; Sanchis, E.; Toniolo, N.; Ur, C.A.; Valiente-Dobon, J.J. url  doi
openurl 
  Title Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array Type Journal Article
  Year 2015 Publication IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 62 Issue 6 Pages 3134-3139  
  Keywords FPGA; front-end electronics; gamma-ray spectroscopy; germanium detectors  
  Abstract In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.53% at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs.  
  Address [Barrientos, D.; Bortolato, D.; Cocconi, P.; Gulmini, M.; Rosso, D.; Toniolo, N.; Valiente-Dobon, J. J.] Ist Nazl Fis Nucl, Lab Nazl Legnaro, I-35020 Padua, Italy, Email: diego.barrientos@lnl.infn.it  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000372013500005 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ pastor @ Serial 2612  
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Author (down) ATLAS Collaboration (Aad, G. et al); Aparisi Pozo, J.A.; Bailey, A.J.; Cabrera Urban, S.; Cardillo, F.; Castillo Gimenez, V.; Costa, M.J.; Escobar, C.; Estrada Pastor, O.; Ferrer, A.; Fiorini, L.; Fullana Torregrosa, E.; Fuster, J.; Garcia, C.; Garcia Navarro, J.E.; Gonzalez de la Hoz, S.; Gonzalvo Rodriguez, G.R.; Guerrero Rojas, J.G.R.; Higon-Rodriguez, E.; Lacasta, C.; Lozano Bahilo, J.J.; Mamuzic, J.; Marti-Garcia, S.; Martinez Agullo, P.; Mitsou, V.A.; Moreno Llacer, M.; Navarro-Gonzalez, J.; Poveda, J.; Prades Ibañez, A.; Ruiz-Martinez, A.; Sabatini, P.; Salt, J.; Sayago Galvan, I.; Soldevila, U.; Sanchez, J.; Torro Pastor, E.; Valero, A.; Valls Ferrer, J.A.; Villaplana Perez, M.; Vos, M. url  doi
openurl 
  Title The ATLAS Fast TracKer system Type Journal Article
  Year 2021 Publication Journal of Instrumentation Abbreviated Journal J. Instrum.  
  Volume 16 Issue 7 Pages P07006 - 61pp  
  Keywords Modular electronics; Online farms and online filtering; Pattern recognition, cluster finding, calibration and fitting methods; Trigger concepts and systems (hardware and software)  
  Abstract The ATLAS Fast TracKer (FTK) was designed to provide full tracking for the ATLAS high-level trigger by using pattern recognition based on Associative Memory (AM) chips and fitting in high-speed field programmable gate arrays. The tracks found by the FTK are based on inputs from all modules of the pixel and silicon microstrip trackers. The as-built FTK system and components are described, as is the online software used to control them while running in the ATLAS data acquisition system. Also described is the simulation of the FTK hardware and the optimization of the AM pattern banks. An optimization for long-lived particles with large impact parameter values is included. A test of the FTK system with the data playback facility that allowed the FTK to be commissioned during the shutdown between Run 2 and Run 3 of the LHC is reported. The resulting tracks from part of the FTK system covering a limited eta-phi region of the detector are compared with the output from the FTK simulation. It is shown that FTK performance is in good agreement with the simulation.  
  Address [Duvnjak, D.; Jackson, P.; Kong, A. X. Y.; Oliver, J. L.; Ruggeri, T. A.; Sharma, A. S.; White, M. J.] Univ Adelaide, Dept Phys, Adelaide, SA, Australia  
  Corporate Author Thesis  
  Publisher IOP Publishing Ltd Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 1748-0221 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000791152800006 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ pastor @ Serial 5225  
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