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Marco-Hernandez, R., Alves, D., Angoletta, M. E., Marqversen, O., Molendijk, J., Oponowicz, E., et al. (2017). The AD and ELENA orbit, trajectory and intensity measurement systems. J. Instrum., 12, P07024–24pp.
Abstract: This paper describes the new Antiproton Decelerator (AD) orbit measurement system and the Extra Low ENergy Antiproton ring (ELENA) orbit, trajectory and intensity measurement system. The AD machine at European Organization for Nuclear Research (CERN) is presently being used to decelerate antiprotons from 3.57 GeV/c to 100 MeV/c for matter vs anti-matter comparative studies. The ELENA machine, presently under commissioning, has been designed to provide an extra deceleration stage down to 13.7 MeV/c. The AD orbit system is based on 32 horizontal and 27 vertical electrostatic Beam Position Monitor (BPM) fitted with existing low noise front-end amplifiers while the ELENA system consists of 24 BPMs equipped with new low-noise head amplifiers. In both systems the front-end amplifiers generate a difference (delta) and a sum (sigma) signal which are sent to the digital acquisition system, placed tens of meters away from the AD or ELENA rings, where they are digitized and further processed. The beam position is calculated by dividing the difference signal by the sum signal either using directly the raw digitized data for measuring the turn-by-turn trajectory in the ELENA system or after down-mixing the signals to baseband for the orbit measurement in both machines. The digitized sigma signal will be used in the ELENA system to calculate the bunched beam intensity and the Schottky parameters with coasting beam after passing through different signal processing chain. The digital acquisition arrangement for both systems is based on the same hardware, also used in the ELENA Low Level Radio Frequency (LLRF) system, which follows the VME Switched Serial (VXS) enhancement of the Versa Module Eurocard 64x extension (VME64x) standard and includes VITA 57 standard Field Programmable Gate Array Mezzanine Card (FMC). The digital acquisition Field Programmable Gate Array (FPGA) andDigital Signal Processor (DSP) firmware sharesmany common functionalities with the LLRF system but has been tailored for this measurement application in particular. Specific control and acquisition software has been developed for these systems. Both systems are installed in AD and ELENA. The AD orbit system currently measures the orbit in AD while the ELENA system is being used in the commissioning of the ELENA ring.
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Esteve, R., Toledo, J. F., Herrero, V., Simon, A., Monrabal, F., Alvarez, V., et al. (2021). The Event Detection System in the NEXT-White Detector. Sensors, 21(2), 673–18pp.
Abstract: This article describes the event detection system of the NEXT-White detector, a 5 kg high pressure xenon TPC with electroluminescent amplification, located in the Laboratorio Subterraneo de Canfranc (LSC), Spain. The detector is based on a plane of photomultipliers (PMTs) for energy measurements and a silicon photomultiplier (SiPM) tracking plane for offline topological event filtering. The event detection system, based on the SRS-ATCA data acquisition system developed in the framework of the CERN RD51 collaboration, has been designed to detect multiple events based on online PMT signal energy measurements and a coincidence-detection algorithm. Implemented on FPGA, the system has been successfully running and evolving during NEXT-White operation. The event detection system brings some relevant and new functionalities in the field. A distributed double event processor has been implemented to detect simultaneously two different types of events thus allowing simultaneous calibration and physics runs. This special feature provides constant monitoring of the detector conditions, being especially relevant to the lifetime and geometrical map computations which are needed to correct high-energy physics events. Other features, like primary scintillation event rejection, or a double buffer associated with the type of event being searched, help reduce the unnecessary data throughput thus minimizing dead time and improving trigger efficiency.
Keywords: xenon TPC; trigger concepts; data acquisition circuits; FPGA
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Gololo, M. G. D., Carrio Argos, F., & Mellado, B. (2022). Tile Computer-on-Module for the ATLAS Tile Calorimeter Phase-II upgrades. J. Instrum., 17(6), P06020–14pp.
Abstract: The Tile PreProcessor (TilePPr) is the core element of the Tile Calorimeter (TileCal) off-detector electronics for High-luminosity Large Hadron Collider (HL-LHC). The TilePPr comprises FPGA-based boards to operate and read out the TileCal on-detector electronics. The Tile Computer on Module (TileCoM) mezzanine is embedded within TilePPr to carry out three main functionalities. These include remote configuration of on-detector electronics and TilePPr FPGAs, interface the TilePPr with the ATLAS Trigger and Data Acquisition (TDAQ) system, and interfacing the TilePPr with the ATLAS Detector Control System (DCS) by providing monitoring data. The TileCoM is a 10-layer board with a Zynq UltraScale+ ZU2CG for processing data, interface components to integrate with TilePPr and the power supply to be connected to the Advanced Telecommunication Computing Architecture carrier. A CentOS embedded Linux is deployed on the TileCoM to implement the required functionalities for the HL-LHC. In this paper we present the hardware and firmware developments of the TileCoM system in terms of remote programming, interface with ATLAS TDAQ system and DCS system.
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Carrio, F. (2022). The Data Acquisition System for the ATLAS Tile Calorimeter Phase-II Upgrade Demonstrator. IEEE Trans. Nucl. Sci., 69(4), 687–695.
Abstract: The tile calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the large hadron collider (LHC). In 2025, the LHC will be upgraded leading to the high luminosity LHC (HL-LHC). The HL-LHC will deliver an instantaneous luminosity up to seven times larger than the LHC nominal luminosity. The ATLAS Phase-II upgrade (2025-2027) will accommodate the subdetectors to the HL-LHC requirements. As part of this upgrade, the majority of the TileCal on-detector and off-detector electronics will be replaced using a new readout strategy, where the on-detector electronics will digitize and transmit digitized detector data to the off-detector electronics at the bunch crossing frequency (40 MHz). In the counting rooms, the off-detector electronics will compute reconstructed trigger objects for the first-level trigger and will store the digitized samples in pipelined buffers until the reception of a trigger acceptance signal. The off-detector electronics will also distribute the LHC clock to the on-detector electronics embedded within the digital data stream. The TileCal Phase-II upgrade project has undertaken an extensive research and development program that includes the development of a Demonstrator module to evaluate the performance of the new clock and readout architecture envisaged for the HL-LHC. The Demonstrator module equipped with the latest version of the on-detector electronics was built and inserted into the ATLAS experiment. The Demonstrator module is operated and read out using a Tile PreProcessor (TilePPr) Demonstrator which enables backward compatibility with the present ATLAS Trigger and Data AcQuisition (TDAQ), and the timing, trigger, and command (TTC) systems. This article describes in detail the main hardware and firmware components of the clock distribution and data acquisition systems for the Demonstrator module, focusing on the TilePPr Demonstrator.
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Carrio, F., Kim, H. Y., Moreno, P., Reed, R., Sandrock, C., Schettino, V., et al. (2014). Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench. J. Instrum., 9, C03023–12pp.
Abstract: The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception.
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ATLAS Collaboration(Aad, G. et al), Aparisi Pozo, J. A., Bailey, A. J., Cabrera Urban, S., Castillo, F. L., Castillo Gimenez, V., et al. (2020). Performance of the ATLAS muon triggers in Run 2. J. Instrum., 15(9), P09015–57pp.
Abstract: The performance of the ATLAS muon trigger system is evaluated with proton-proton (pp) and heavy-ion (HI) collision data collected in Run 2 during 2015-2018 at the Large Hadron Collider. It is primarily evaluated using events containing a pair of muons from the decay of Z bosons to cover the intermediate momentum range between 26 GeV and 100 GeV. Overall, the efficiency of the single-muon triggers is about 68% in the barrel region and 85% in the endcap region. The p(T) range for efficiency determination is extended by using muons from decays of J/psi mesons, W bosons, and top quarks. The performance in HI collision data is measured and shows good agreement with the results obtained in pp collisions. The muon trigger shows uniform and stable performance in good agreement with the prediction of a detailed simulation. Dedicated multi-muon triggers with kinematic selections provide the backbone to beauty, quarkonia, and low-mass physics studies. The design, evolution and performance of these triggers are discussed in detail.
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Aliaga, R. J., Herrero-Bosch, V., Capra, S., Pullia, A., Duenas, J. A., Grassi, L., et al. (2015). Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC. Nucl. Instrum. Methods Phys. Res. A, 800, 34–39.
Abstract: The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling, Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.
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KM3NeT Collaboration(Aiello, S. et al), Calvo, D., Coleiro, A., Colomer, M., Gozzini, S. R., Hernandez-Rey, J. J., et al. (2020). The Control Unit of the KM3NeT Data Acquisition System. Comput. Phys. Commun., 256, 107433–16pp.
Abstract: The KM3NeT Collaboration runs a multi-site neutrino observatory in the Mediterranean Sea. Water Cherenkov particle detectors, deep in the sea and far off the coasts of France and Italy, are already taking data while incremental construction progresses. Data Acquisition Control software is operating off-shore detectors as well as testing and qualification stations for their components. The software, named Control Unit, is highly modular. It can undergo upgrades and reconfiguration with the acquisition running. Interplay with the central database of the Collaboration is obtained in a way that allows for data taking even if Internet links fail. In order to simplify the management of computing resources in the long term, and to cope with possible hardware failures of one or more computers, the KM3NeT Control Unit software features a custom dynamic resource provisioning and failover technology, which is especially important for ensuring continuity in case of rare transient events in multi-messenger astronomy. The software architecture relies on ubiquitous tools and broadly adopted technologies and has been successfully tested on several operating systems.
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Valero, A., Castillo Gimenez, V., Ferrer, A., Gonzalez, V., Hernandez Jimenez, Y., Higon-Rodriguez, E., et al. (2011). The ATLAS tile calorimeter ROD injector and multiplexer board. Nucl. Instrum. Methods Phys. Res. A, 629(1), 74–79.
Abstract: The ATLAS Tile Calorimeter is a sampling detector composed by cells made of iron-scintillator tiles. The calorimeter cell signals are digitized in the front-end electronics and transmitted to the Read-Out Drivers (RODs) at the first level trigger rate. The ROD receives triggered data from up to 9856 channels and provides the energy, phase and quality factor of the signals to the second level trigger. The back-end electronics is divided into four partitions containing eight RODs each. Therefore, a total of 32 RODs are used to process and transmit the data of the TileCal detector. In order to emulate the detector signals in the production and commissioning of ROD modules a board called ROD Injector and Multiplexer Board (RIMBO) was designed. In this paper, the RIMBO main functional blocks, PCB design and the different operation modes are described. It is described the crucial role of the board within the TileCal ROD test-bench in order to emulate the front-end electronics during the validation of ROD boards as well as during the evaluation of the ROD signal reconstruction algorithms. Finally, qualification and performance results for the injection operation mode obtained during the Tile Calorimeter ROD production tests are presented.
Keywords: LHC; ATLAS; Calorimeter; Data acquisition; FPGA; Bit error rate
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ATLAS Collaboration(Aad, G. et al), Aparisi Pozo, J. A., Bailey, A. J., Cabrera Urban, S., Castillo, F. L., Castillo Gimenez, V., et al. (2020). Operation of the ATLAS trigger system in Run 2. J. Instrum., 15(10), P10004–59pp.
Abstract: The ATLAS experiment at the Large Hadron Collider employs a two-level trigger system to record data at an average rate of 1 kHz from physics collisions, starting from an initial bunch crossing rate of 40 MHz. During the LHC Run 2 (2015-2018), the ATLAS trigger system operated successfully with excellent performance and flexibility by adapting to the various run conditions encountered and has been vital for the ATLAS Run-2 physics programme For proton-proton running, approximately 1500 individual event selections were included in a trigger menu which specified the physics signatures and selection algorithms used for the data-taking, and the allocated event rate and bandwidth. The trigger menu must reflect the physics goals for a given data collection period, taking into account the instantaneous luminosity of the LHC and limitations from the ATLAS detector readout, online processing farm, and offline storage. This document discusses the operation of the ATLAS trigger system during the nominal proton-proton data collection in Run 2 with examples of special data-taking runs. Aspects of software validation, evolution of the trigger selection algorithms during Run 2, monitoring of the trigger system and data quality as well as trigger configuration are presented.
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