| Records |
| Author |
Dimmock, M.R.; Nikulin, D.A.; Gillam, J.E.; Nguyen, C.V. |
| Title |
An OpenCL Implementation of Pinhole Image Reconstruction |
Type |
Journal Article |
| Year |
2012 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
| Volume |
59 |
Issue |
4 |
Pages |
1738-1749 |
| Keywords |
Collimator; GPU; OpenCL; pinhole |
Abstract  |
AC++/OpenCL software platform for emission image reconstruction of data from pinhole cameras has been developed. The software incorporates a new, accurate but computationally costly, probability distribution function for operating on list-mode data from detector stacks. The platform architecture is more general than previous works, supporting advanced models such as arbitrary probability distribution, collimation geometry and detector stack geometry. The software was implemented such that all performance-critical operations occur on OpenCL devices, generally GPUs. The performance of the software is tested on several commodity CPU and GPU devices. |
| Address |
[Dimmock, Matthew R.; Nikulin, Dmitri A.; Nguyen, Chuong V.] Monash Univ, Sch Phys, Melbourne, Vic 3800, Australia, Email: matthew.dimmock@synchrotron.org.au; |
| Corporate Author |
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Thesis |
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| Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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| Language |
English |
Summary Language |
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Original Title |
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| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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| ISSN |
0018-9499 |
ISBN |
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Medium |
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| Area |
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Expedition |
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Conference |
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| Notes |
WOS:000307893900034 |
Approved |
no |
| Is ISI |
yes |
International Collaboration |
yes |
| Call Number |
IFIC @ pastor @ |
Serial |
1145 |
| Permanent link to this record |
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| Author |
Aliaga, R.J. |
| Title |
Real-Time Estimation of Zero Crossings of Sampled Signals for Timing Using Cubic Spline Interpolation |
Type |
Journal Article |
| Year |
2017 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
| Volume |
64 |
Issue |
8 |
Pages |
2414-2422 |
| Keywords |
Digital arithmetic; digital circuits; digital timing; field-programmable gate array (FPGA); interpolation; signal processing algorithms; splines time estimation; time resolution |
| Abstract |
A scheme is proposed for hardware estimation of the location of zero crossings of sampled signals with subsample resolution for timing applications, which consists of interpolating the signal with a cubic spline near the zero crossing and then finding the root of the resulting polynomial. An iterative algorithm based on the bisection method is presented that obtains one bit of the result per step and admits an efficient digital implementation using fixed-point representation. In particular, the root estimation iteration involves only two additions, and the initial values can be obtained from finite impulse response (FIR) filters with certain symmetry properties. It is shown that this allows online real-time estimation of timestamps in free-running sampling detector systems with improved accuracy with respect to the more common linear interpolation. The method is evaluated with simulations using ideal and real timing signals, and estimates are given for the resource usage and speed of its implementation. |
| Address |
[Aliaga, Ramon J.] Inst Fis Corpuscular, Paterna 46980, Spain, Email: raalva@upvnet.upv.es |
| Corporate Author |
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Thesis |
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| Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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| Language |
English |
Summary Language |
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Original Title |
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| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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| ISSN |
0018-9499 |
ISBN |
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Medium |
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| Area |
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Expedition |
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Conference |
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| Notes |
WOS:000411027700008 |
Approved |
no |
| Is ISI |
yes |
International Collaboration |
no |
| Call Number |
IFIC @ pastor @ |
Serial |
3301 |
| Permanent link to this record |
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| Author |
Marco-Hernandez, R.; Bau, M.; Ferrari, M.; Ferrari, V.; Pedersen, F.; Soby, L. |
| Title |
A Low-Noise Charge Amplifier for the ELENA Trajectory, Orbit, and Intensity Measurement System |
Type |
Journal Article |
| Year |
2017 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
| Volume |
64 |
Issue |
9 |
Pages |
2465-2473 |
| Keywords |
Beam position monitor (BPM); charge sensitive amplifier; instrumentation for accelerators; low-noise amplifier; particle accelerators; printed circuits |
| Abstract |
A low-noise head amplifier has been developed for the extra low energy antiproton ring beam trajectory, orbit, and intensity measurement system at CERN. This system is based on 24 double-electrode electrostatic beam position monitors installed around the ring. A head amplifier is placed close to each beam position monitor to amplify the electrode signals and generate a difference and a sum signal. These signals are sent to the digital acquisition system, about 50 m away from the ring, where they are digitized and further processed. The beam position can be measured by dividing the difference signal by the sum signal while the sum signal gives information relative to the beam intensity. The head amplifier consists of two discrete charge preamplifiers with junction field effect transistor (JFET) inputs, a sum and a difference stage, and two cable drivers. Special attention has been paid to the amplifier printed circuit board design to minimize the parasitic capacitances and inductances at the charge amplifier stages to meet the gain and noise requirements. The measurements carried out on the head amplifier showed a gain of 40.5 and 46.5 dB for the sum and difference outputs with a bandwidth from 200 Hz to 75 MHz and an input voltage noise density lower than 400 pV/v Hz. Twenty head amplifiers have been already installed in the ring and they have been used to detect the first beam signals during the first commissioning stage in November 2016. |
| Address |
[Marco-Hernandez, Ricardo; Pedersen, Flemming; Soby, Lars] CERN, CH-1217 Meyrin, Switzerland, Email: rmarco@ific.uv.es |
| Corporate Author |
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Thesis |
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| Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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| Language |
English |
Summary Language |
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Original Title |
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| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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| ISSN |
0018-9499 |
ISBN |
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Medium |
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| Area |
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Expedition |
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Conference |
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| Notes |
WOS:000411029500002 |
Approved |
no |
| Is ISI |
yes |
International Collaboration |
yes |
| Call Number |
IFIC @ pastor @ |
Serial |
3298 |
| Permanent link to this record |
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| Author |
Belver, D.; Cabanelas, P.; Castro, E.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. |
| Title |
Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall |
Type |
Journal Article |
| Year |
2010 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
| Volume |
57 |
Issue |
5 |
Pages |
2848-2856 |
| Keywords |
Charge to width algorithm; fast amplifying and digitizing electronics; front-end electronics; HADES; time of flight; timing RPC |
| Abstract |
A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m(2) divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel Daughter BOard(DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade [1]. The commissioning of the whole RPC wall is finished and the 6 sectors are already mounted in their final position in the HADES spectrometer and ready to take data during the beam-times foreseen for 2010. |
| Address |
[Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.] Univ Santiago Compostela, LabCAF, Santiago De Compostela 15782, Spain, Email: daniel.belver@usc.es |
| Corporate Author |
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Thesis |
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| Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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| Language |
English |
Summary Language |
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Original Title |
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| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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| ISSN |
0018-9499 |
ISBN |
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Medium |
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| Area |
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Expedition |
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Conference |
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| Notes |
ISI:000283440400007 |
Approved |
no |
| Is ISI |
yes |
International Collaboration |
yes |
| Call Number |
IFIC @ elepoucu @ |
Serial |
349 |
| Permanent link to this record |
