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Author Egea Canet, F.J. et al; Gadea, A.; Huyuk, T. doi  openurl
  Title A New Front-End High-Resolution Sampling Board for the New-Generation Electronics of EXOGAM2 and NEDA Detectors Type Journal Article
  Year 2015 Publication IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 62 Issue 3 Pages 1056-1062  
  Keywords Acquisition in HP-Ge detectors; high-speed ADCs; low-noise electronics design  
  Abstract (down) This paper presents the final design and results of the FADC Mezzanine for the EXOGAM (EXOtic GAMma array spectrometer) and NEDA (Neutron Detector Array) detectors. The measurements performed include those of studying the effective number of bits, the energy resolution using HP-Ge detectors, as well as timing histograms and discrimination performance. Finally, the conclusion shows how a common digitizing device has been integrated in the experimental environment of two very different detectors which combine both low-noise acquisition and fast sampling rates. Not only the integration fulfilled the expected specifications on both systems, but it also showed how a study of synergy between detectors could lead to the reduction of resources and time by applying a common strategy.  
  Address [Egea Canet, F. J.; Gonzalez, V.; Sanchis, E.] Univ Valencia, Dept Elect Engn, Escola Tecn Super Engn, Valencia, Spain, Email: jaegea@ific.uv.es  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000356458000028 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ pastor @ Serial 2278  
Permanent link to this record
 

 
Author Egea Canet, F.J. et al; Gadea, A.; Huyuk, T. doi  openurl
  Title Digital Front-End Electronics for the Neutron Detector NEDA Type Journal Article
  Year 2015 Publication IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 62 Issue 3 Pages 1063-1069  
  Keywords Digital systems; front-end electronics; neutron detectors; neutron-gamma discrimination  
  Abstract (down) This paper presents the design of the NEDA (Neutron Detector Array) electronics, a first attempt to involve the use of digital electronics in large neutron detector arrays. Starting from the front-end modules attached to the PMTs (PhotoMultiplier Tubes) and ending up with the data processing workstations, a comprehensive electronic system capable of dealing with the acquisition and pre-processing of the neutron array is detailed. Among the electronic modules required, we emphasize the front-end analog processing, the digitalization, digital pre-processing and communications firmware, as well as the integration of the GTS (Global Trigger and Synchronization) system, already used successfully in AGATA (Advanced Gamma Tracking Array). The NEDA array will be available for measurements in 2016.  
  Address [Egea Canet, F. J.; Gonzalez, V.; Sanchis, E.] Univ Valencia, Dept Elect Engn, Escola Tecn Super Engn, Valencia, Spain, Email: jaegea@ific.uv.es  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000356458000029 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ pastor @ Serial 2279  
Permanent link to this record
 

 
Author Carrio, F.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Higon-Rodriguez, E.; Marin, C.; Moreno, P.; Sanchis, E.; Solans, C.; Valero, A.; Valls Ferrer, J.A. doi  openurl
  Title Optical Link Card Design for the Phase II Upgrade of TileCal Experiment Type Journal Article
  Year 2011 Publication IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 58 Issue 4 Pages 1657-1663  
  Keywords High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices  
  Abstract (down) This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol.  
  Address [Carrio, F; Gonzalez, V; Marin, C; Sanchis, E] Univ Valencia, Dept Elect Engn, E-46100 Valencia, Spain, Email: vicente.gonzalez@uv.es  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000293975700037 Approved no  
  Is ISI yes International Collaboration no  
  Call Number IFIC @ elepoucu @ Serial 722  
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Author Alvarez, V.; Herrero-Bosch, V.; Esteve, R.; Laing, A.; Rodriguez, J.; Querol, M.; Monrabal, F.; Toledo, J.F.; Gomez-Cadenas, J.J. url  doi
openurl 
  Title The electronics of the energy plane of the NEXT-White detector Type Journal Article
  Year 2019 Publication Nuclear Instruments & Methods in Physics Research A Abbreviated Journal Nucl. Instrum. Methods Phys. Res. A  
  Volume 917 Issue Pages 68-76  
  Keywords Calorimetry; Front-end electronics; Digital baseline restoration  
  Abstract (down) This paper describes the electronics of NEXT-White (NEW) detector PMT plane, a high pressure xenon TPC with electroluminescent amplification (HPXe-EL) currently operating at the Laboratorio Subterraneo de Canfranc (LSC) in Huesca, Spain. In NEXT-White the energy of the event is measured by a plane of photomultipliers (PMTs) located behind a transparent cathode. The PMTs are Hamamatsu R11410-10 chosen due to their low radioactivity. The electronics have been designed and implemented to fulfill strict requirements: an overall energy resolution below 1% and a radiopurity budget of 20 mBq unit(-1) in the chain of Bi-214. All the components and materials have been carefully screened to assure a low radioactivity level and at the same time meet the required front-end electronics specifications. In order to reduce low frequency noise effects and enhance detector safety a grounded cathode connection has been used for the PMTs. This implies an AC-coupled readout and baseline variations in the PMT signals. A detailed description of the electronics and a novel approach based on a digital baseline restoration to obtain a linear response and handle AC coupling effects is presented. The final PMT channel design has been characterized with linearity better than 0.4% and noise below 0.4 mV.  
  Address [Alvarez, V; Laing, A.; Rodriguez, J.; Querol, M.; Gomez-Cadenas, J. J.] CSIC, IFIC, Inst Fis Corpuscular, Calle Catedrat Jose Beltran 2, Valencia 46980, Spain, Email: vicente.alvarez@ific.uv.es  
  Corporate Author Thesis  
  Publisher Elsevier Science Bv Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0168-9002 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000455016500010 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ pastor @ Serial 3868  
Permanent link to this record
 

 
Author Carrio, F. doi  openurl
  Title The Data Acquisition System for the ATLAS Tile Calorimeter Phase-II Upgrade Demonstrator Type Journal Article
  Year 2022 Publication IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 69 Issue 4 Pages 687-695  
  Keywords Large Hadron Collider; Data acquisition; Field programmable gate arrays; Clocks; Detectors; Computer architecture; Microprocessors; ATLAS tile calorimeter (TileCal); data acquisition (DAQ) systems; field-programmable gate array (FPGA); high energy physics; high-speed electronics  
  Abstract (down) The tile calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the large hadron collider (LHC). In 2025, the LHC will be upgraded leading to the high luminosity LHC (HL-LHC). The HL-LHC will deliver an instantaneous luminosity up to seven times larger than the LHC nominal luminosity. The ATLAS Phase-II upgrade (2025-2027) will accommodate the subdetectors to the HL-LHC requirements. As part of this upgrade, the majority of the TileCal on-detector and off-detector electronics will be replaced using a new readout strategy, where the on-detector electronics will digitize and transmit digitized detector data to the off-detector electronics at the bunch crossing frequency (40 MHz). In the counting rooms, the off-detector electronics will compute reconstructed trigger objects for the first-level trigger and will store the digitized samples in pipelined buffers until the reception of a trigger acceptance signal. The off-detector electronics will also distribute the LHC clock to the on-detector electronics embedded within the digital data stream. The TileCal Phase-II upgrade project has undertaken an extensive research and development program that includes the development of a Demonstrator module to evaluate the performance of the new clock and readout architecture envisaged for the HL-LHC. The Demonstrator module equipped with the latest version of the on-detector electronics was built and inserted into the ATLAS experiment. The Demonstrator module is operated and read out using a Tile PreProcessor (TilePPr) Demonstrator which enables backward compatibility with the present ATLAS Trigger and Data AcQuisition (TDAQ), and the timing, trigger, and command (TTC) systems. This article describes in detail the main hardware and firmware components of the clock distribution and data acquisition systems for the Demonstrator module, focusing on the TilePPr Demonstrator.  
  Address [Carrio, F.] Inst Fis Corpuscular CSIC UV, Paterna 46980, Spain, Email: fernando.carrio@cern.ch  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000803113800016 Approved no  
  Is ISI yes International Collaboration no  
  Call Number IFIC @ pastor @ Serial 5244  
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