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Author  |
Valero, A.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Hernandez Jimenez, Y.; Higon-Rodriguez, E.; Sanchis, E.; Solans, C.; Torres, J.; Valls Ferrer, J.A. |
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Title |
The ATLAS tile calorimeter ROD injector and multiplexer board |
Type |
Journal Article |
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Year |
2011 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
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Volume |
629 |
Issue |
1 |
Pages |
74-79 |
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Keywords |
LHC; ATLAS; Calorimeter; Data acquisition; FPGA; Bit error rate |
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Abstract |
The ATLAS Tile Calorimeter is a sampling detector composed by cells made of iron-scintillator tiles. The calorimeter cell signals are digitized in the front-end electronics and transmitted to the Read-Out Drivers (RODs) at the first level trigger rate. The ROD receives triggered data from up to 9856 channels and provides the energy, phase and quality factor of the signals to the second level trigger. The back-end electronics is divided into four partitions containing eight RODs each. Therefore, a total of 32 RODs are used to process and transmit the data of the TileCal detector. In order to emulate the detector signals in the production and commissioning of ROD modules a board called ROD Injector and Multiplexer Board (RIMBO) was designed. In this paper, the RIMBO main functional blocks, PCB design and the different operation modes are described. It is described the crucial role of the board within the TileCal ROD test-bench in order to emulate the front-end electronics during the validation of ROD boards as well as during the evaluation of the ROD signal reconstruction algorithms. Finally, qualification and performance results for the injection operation mode obtained during the Tile Calorimeter ROD production tests are presented. |
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Address |
[Valero, A.; Castillo, V.; Ferrer, A.; Hernandez, Y.; Higon, E.; Solans, C.; Valls, J. A.] Univ Valencia, CSIC, Inst Fis Corpuscular, Valencia 46071, Spain, Email: alberto.valero@cern.ch |
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Publisher |
Elsevier Science Bv |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0168-9002 |
ISBN |
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Medium |
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Expedition |
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Conference |
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Notes |
ISI:000287556100012 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
no |
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Call Number |
IFIC @ pastor @ |
Serial |
555 |
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Author |
Ortiz Arciniega, J.L.; Carrio, F.; Valero, A. |
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Title |
FPGA implementation of a deep learning algorithm for real-time signal reconstruction in particle detectors under high pile-up conditions |
Type |
Journal Article |
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Year |
2019 |
Publication |
Journal of Instrumentation |
Abbreviated Journal |
J. Instrum. |
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Volume |
14 |
Issue |
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Pages |
P09002 - 13pp |
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Keywords |
Data processing methods; Pattern recognition; cluster finding; calibration and fitting methods; Simulation methods and programs |
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Abstract |
The analog signals generated in the read-out electronics of particle detectors are shaped prior to the digitization in order to improve the signal to noise ratio (SNR). The real amplitude of the analog signal is then obtained using digital filters, which provides information about the energy deposited in the detector. The classical digital filters have a good performance in ideal situations with Gaussian electronic noise and no pulse shape distortion. However, high-energy particle colliders, such as the Large Hadron Collider (LHC) at CERN, can produce multiple simultaneous events, which produce signal pileup. The performance of classical digital filters deteriorates in these conditions since the signal pulse shape gets distorted. In addition, this type of experiments produces a high rate of collisions, which requires high throughput data acquisitions systems. In order to cope with these harsh requirements, new read-out electronics systems are based on high-performance FPGAs, which permit the utilization of more advanced real-time signal reconstruction algorithms. In this paper, a deep learning method is proposed for real-time signal reconstruction in high pileup particle detectors. The performance of the new method has been studied using simulated data and the results are compared with a classical FIR filter method. In particular, the signals and FIR filter used in the ATLAS Tile Calorimeter are used as benchmark. The implementation, resources usage and performance of the proposed Neural Network algorithm in FPGA are also presented. |
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Address |
[Ortiz Arciniega, J. L.] Univ Valencia, Avinguda Univ S-N, Burjassot, Spain, Email: orarjo@alumni.uv.es |
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Thesis |
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Publisher |
Iop Publishing Ltd |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
1748-0221 |
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Area |
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Expedition |
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Conference |
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Notes |
WOS:000486990000002 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
no |
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Call Number |
IFIC @ pastor @ |
Serial |
4150 |
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Author |
Cervello, A.; Carrio, F.; Garcia, R.; Martos, J.; Soret, J.; Torres, J.; Valero, A. |
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Title |
The TileCal PreProcessor interface with the ATLAS global data acquisition system at the HL-LHC |
Type |
Journal Article |
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Year |
2022 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
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Volume |
1043 |
Issue |
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Pages |
167492 - 2pp |
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Keywords |
ATLAS; Tile Calorimeter; HL-LHC; TilePPr; FELIX; SWROD; DAQ |
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Abstract |
The Large Hadron Collider (LHC) has envisaged a series of upgrades towards a High Luminosity LHC (HL-LHC) delivering five times the LHC nominal instantaneous luminosity. It will take place throughout 2026-2028, corresponding to the Long Shutdown 3. During this upgrade, the ATLAS Tile Hadronic Calorimeter (TileCal) will replace completely on-and off-detector electronics adopting a new read-out architecture. Signals captured from TileCal are digitized by the on-detector electronics and transmitted to the TileCal PreProcessor (TilePPr) located off-detector, which provides the interface with the ATLAS trigger and data acquisition systems.TilePPr receives, process and transmits the data from the on-detector system and transmits it to the Front -End Link eXchange (FELIX) system. FELIX is the ATLAS common hardware in all the subdetectors designed to act as a data router, receiving and forwarding data to the SoftWare Read-Out Driver (SWROD) computers. FELIX also distributes the Timing, Trigger and Control (TTC) signals to the TilePPr to be propagated to the on-detector electronics. The SWROD is an ATLAS common software solution to perform detector specific data processing, including configuration, calibration, control and monitoring of the partitionIn this contribution we will introduce the new read-out elements for TileCal at the HL-LHC, the intercon-nection between the off-detector electronics and the FELIX system, the configuration and implementation for the test beam campaigns, as well as future developments of the preprocessing and monitoring status of the calorimeter modules through the SWROD infrastructure. |
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Address |
[Cervello, Antonio; Carrio, Fernando; Valero, Alberto] UV, CSIC, Inst Fis Corpuscular, Carrer Catedrat Jose Beltran Martinez 2, Valencia 46980, Spain, Email: antonio.cervello@uv.es |
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Corporate Author |
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Thesis |
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Publisher |
Elsevier |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0168-9002 |
ISBN |
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Medium |
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Area |
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Expedition |
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Conference |
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Notes |
WOS:000868495700012 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
no |
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Call Number |
IFIC @ pastor @ |
Serial |
5399 |
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Author |
Carrio, F.; Kim, H.Y.; Moreno, P.; Reed, R.; Sandrock, C.; Schettino, V.; Shalyugin, A.; Solans, C.; Souza, J.; Usai, G.; Valero, A. |
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Title |
Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench |
Type |
Journal Article |
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Year |
2014 |
Publication |
Journal of Instrumentation |
Abbreviated Journal |
J. Instrum. |
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Volume |
9 |
Issue |
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Pages |
C03023 - 12pp |
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Keywords |
Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms; databases); Data acquisition concepts; Digital electronic circuits |
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Abstract |
The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception. |
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Address |
[Carrio, F.; Valero, A.] Univ Valencia, CSIC, Inst Fis Corpuscular, E-46980 Paterna, Spain, Email: fernando.carrio@cern.ch |
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Corporate Author |
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Thesis |
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Publisher |
Iop Publishing Ltd |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
1748-0221 |
ISBN |
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Medium |
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Area |
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Expedition |
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Conference |
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Notes |
WOS:000336123200023 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
1801 |
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| Permanent link to this record |
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Author |
Carrio, F.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Higon-Rodriguez, E.; Marin, C.; Moreno, P.; Sanchis, E.; Solans, C.; Valero, A.; Valls Ferrer, J.A. |
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Title |
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment |
Type |
Journal Article |
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Year |
2011 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
58 |
Issue |
4 |
Pages |
1657-1663 |
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Keywords |
High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices |
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Abstract |
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol. |
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Address |
[Carrio, F; Gonzalez, V; Marin, C; Sanchis, E] Univ Valencia, Dept Elect Engn, E-46100 Valencia, Spain, Email: vicente.gonzalez@uv.es |
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Corporate Author |
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Thesis |
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Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0018-9499 |
ISBN |
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Area |
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Expedition |
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Conference |
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Notes |
WOS:000293975700037 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
no |
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Call Number |
IFIC @ elepoucu @ |
Serial |
722 |
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