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Modamio, V., Valiente-Dobon, J. J., Jaworski, G., Huyuk, T., Triossi, A., Egea, J., et al. (2015). Digital pulse-timing technique for the neutron detector array NEDA. Nucl. Instrum. Methods Phys. Res. A, 775, 71–76.
Abstract: A new digital pulse-timing algorithm, to be used with the future neutron detector array NEDA, has been developed and tested. The time resolution of four 5 in diameter photomultiplier tubes (XP4512, R4144, R11833-100, and ET9390-kb), coupled to a cylindrical 5 in by 5 in BC501A liquict scintillator detector was measured by employing digital sampling electronics and a constant fraction discriminator (CFD) algorithm. The zero crossing of the CM algorithm was obtained with a cubic spline interpolation, which was continuous up to the second derivative. The performance of the algorithm was studied at sampling rates of 500 MS/s and 200 MS/s. The time resolution obtained with the digital electronics was compared to the values acquired with a standard analog CFD. The result of this comparison shows that the time resolution from the analog and the digital measurements at 500 MS/s and at 200 MS/s are within 15% for all the tested photomultiplier tubes.
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Aliaga, R. J., Herrero-Bosch, V., Capra, S., Pullia, A., Duenas, J. A., Grassi, L., et al. (2015). Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC. Nucl. Instrum. Methods Phys. Res. A, 800, 34–39.
Abstract: The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling, Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.
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