Records |
Author |
Barrio, J.; Etxebeste, A.; Lacasta, C.; Muñoz, E.; Oliver, J.F.; Solaz, C.; Llosa, G. |
Title ![sorted by Title field, descending order (down)](img/sort_desc.gif) |
Performance of VATA64HDR16 ASIC for medical physics applications based on continuous crystals and SiPMs |
Type |
Journal Article |
Year |
2015 |
Publication |
Journal of Instrumentation |
Abbreviated Journal |
J. Instrum. |
Volume |
10 |
Issue |
|
Pages |
P12001 - 12pp |
Keywords |
Solid state detectors; Photon detectors for UV, visible and IR photons (solid-state) (PIN diodes, APDs, Si-PMTs, G-APDs, CCDs, EBCCDs, EMCCDs etc); Front-end electronics for detector readout; Gamma detectors (scintillators, CZT, HPG, HgI etc) |
Abstract |
Detectors based on Silicon Photomultipliers (SiPMs) coupled to continuous crystals are being tested in medical physics applications due to their potential high resolution and sensitivity. To cope with the high granularity required for a very good spatial resolution, SiPM matrices with a large amount of elements are needed. To be able to read the information coming from each individual channel, dedicated ASICs are employed. The VATA64HDR16 ASIC is a 64-channel, charge-sensitive amplifier that converts the collected charge into a proportional current or voltage signal. A complete assessment of the suitability of that ASIC for medical physics applications based on continuous crystals and SiPMs has been carried out. The input charge range is linear from 20 pC up to 55 pC. The energy resolution obtained at 511 keV is 10% FWHM with a LaBr3 crystal and 16% FWHM with a LYSO crystal. A coincidence timing resolution of 24 ns FWHM is obtained with two LYSO crystals. |
Address |
[Barrio, J.; Etxebeste, A.; Lacasta, C.; Munoz, E.; Oliver, J. F.; Solaz, C.; Llosa, G.] Univ Valencia, CSIC, Inst Fis Corpuscular, Parque Cient,C Catedrat Jose Beltran 2, E-46980 Paterna, Spain, Email: John.Barrio@ific.uv.es |
Corporate Author |
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Thesis |
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Publisher |
Iop Publishing Ltd |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
1748-0221 |
ISBN |
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Medium |
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Area |
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Expedition |
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Conference |
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Notes |
WOS:000369998500034 |
Approved |
no |
Is ISI |
yes |
International Collaboration |
no |
Call Number |
IFIC @ pastor @ |
Serial |
2548 |
Permanent link to this record |
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Author |
Belver, D.; Cabanelas, P.; Castro, E.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. |
Title ![sorted by Title field, descending order (down)](img/sort_desc.gif) |
Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall |
Type |
Journal Article |
Year |
2010 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
Volume |
57 |
Issue |
5 |
Pages |
2848-2856 |
Keywords |
Charge to width algorithm; fast amplifying and digitizing electronics; front-end electronics; HADES; time of flight; timing RPC |
Abstract |
A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m(2) divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel Daughter BOard(DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade [1]. The commissioning of the whole RPC wall is finished and the 6 sectors are already mounted in their final position in the HADES spectrometer and ready to take data during the beam-times foreseen for 2010. |
Address |
[Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.] Univ Santiago Compostela, LabCAF, Santiago De Compostela 15782, Spain, Email: daniel.belver@usc.es |
Corporate Author |
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Thesis |
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Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0018-9499 |
ISBN |
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Medium |
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Area |
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Expedition |
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Conference |
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Notes |
ISI:000283440400007 |
Approved |
no |
Is ISI |
yes |
International Collaboration |
yes |
Call Number |
IFIC @ elepoucu @ |
Serial |
349 |
Permanent link to this record |
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Author |
Barrientos, D.; Bellato, M.; Bazzacco, D.; Bortolato, D.; Cocconi, P.; Gadea, A.; Gonzalez, V.; Gulmini, M.; Isocrate, R.; Mengoni, D.; Pullia, A.; Recchia, F.; Rosso, D.; Sanchis, E.; Toniolo, N.; Ur, C.A.; Valiente-Dobon, J.J. |
Title ![sorted by Title field, descending order (down)](img/sort_desc.gif) |
Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array |
Type |
Journal Article |
Year |
2015 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
Volume |
62 |
Issue |
6 |
Pages |
3134-3139 |
Keywords |
FPGA; front-end electronics; gamma-ray spectroscopy; germanium detectors |
Abstract |
In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.53% at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs. |
Address |
[Barrientos, D.; Bortolato, D.; Cocconi, P.; Gulmini, M.; Rosso, D.; Toniolo, N.; Valiente-Dobon, J. J.] Ist Nazl Fis Nucl, Lab Nazl Legnaro, I-35020 Padua, Italy, Email: diego.barrientos@lnl.infn.it |
Corporate Author |
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Thesis |
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Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0018-9499 |
ISBN |
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Medium |
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Area |
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Expedition |
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Conference |
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Notes |
WOS:000372013500005 |
Approved |
no |
Is ISI |
yes |
International Collaboration |
yes |
Call Number |
IFIC @ pastor @ |
Serial |
2612 |
Permanent link to this record |
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Author |
ANTARES Collaboration (Aguilar, J.A. et al); Bigongiari, C.; Dornic, D.; Emanuele, U.; Gomez-Gonzalez, J.P.; Hernandez-Rey, J.J.; Mangano, S.; Salesa, F.; Toscano, S.; Yepes, H.; Zornoza, J.D.; Zuñiga, J. |
Title ![sorted by Title field, descending order (down)](img/sort_desc.gif) |
Performance of the front-end electronics of the ANTARES neutrino telescope |
Type |
Journal Article |
Year |
2010 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
Volume |
622 |
Issue |
1 |
Pages |
59-73 |
Keywords |
Neutrino telescope; Photomultiplier tube; Front-end electronics; ASIC |
Abstract |
ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip: results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated. |
Address |
[Aguilar, J. A.; Bigongiari, C.; Dornic, D.; Emanuele, U.; Gomez-Gonzalez, J. P.; Hernandez-Rey, J. J.; Mangano, S.; Salesa, F.; Toscano, S.; Yepes, H.; Zornoza, J. D.; Zuniga, J.] Univ Valencia, IFIC, CSIC, Valencia 46071, Spain, Email: s.loucatos@cea.fr |
Corporate Author |
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Thesis |
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Publisher |
Elsevier Science Bv |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0168-9002 |
ISBN |
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Medium |
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Area |
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Expedition |
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Conference |
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Notes |
ISI:000282530300009 |
Approved |
no |
Is ISI |
yes |
International Collaboration |
yes |
Call Number |
IFIC @ elepoucu @ |
Serial |
363 |
Permanent link to this record |
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Author |
Carrio, F.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Higon-Rodriguez, E.; Marin, C.; Moreno, P.; Sanchis, E.; Solans, C.; Valero, A.; Valls Ferrer, J.A. |
Title ![sorted by Title field, descending order (down)](img/sort_desc.gif) |
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment |
Type |
Journal Article |
Year |
2011 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
Volume |
58 |
Issue |
4 |
Pages |
1657-1663 |
Keywords |
High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices |
Abstract |
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol. |
Address |
[Carrio, F; Gonzalez, V; Marin, C; Sanchis, E] Univ Valencia, Dept Elect Engn, E-46100 Valencia, Spain, Email: vicente.gonzalez@uv.es |
Corporate Author |
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Thesis |
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Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0018-9499 |
ISBN |
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Medium |
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Area |
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Expedition |
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Conference |
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Notes |
WOS:000293975700037 |
Approved |
no |
Is ISI |
yes |
International Collaboration |
no |
Call Number |
IFIC @ elepoucu @ |
Serial |
722 |
Permanent link to this record |