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Author |
Poley, L. et al; Bernabeu, J.; Civera, J.V.; Lacasta, C.; Leon, P.; Platero, A.; Platero, V; Solaz, C.; Soldevila, U.; Vidal, G. |
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Title |
The ABC130 barrel module prototyping programme for the ATLAS strip tracker |
Type |
Journal Article |
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Year |
2020 |
Publication |
Journal of Instrumentation |
Abbreviated Journal |
J. Instrum. |
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Volume |
15 |
Issue |
9 |
Pages |
P09004 - 78pp |
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Keywords |
Detector design and construction technologies and materials; Si microstrip and pad detectors; Radiation-hard detectors; Front-end electronics for detector readout |
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Abstract |
For the Phase-II Upgrade of the ATLAS Detector [1], its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100% silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: an early program using readout chips designed using a 250 nm fabrication process (ABCN-250) [2, 3] and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests. |
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Address |
[Poley, L.; Anderssen, E.; Ciocio, A.; Cornell, E.; Haber, C.; Haugen, T. E.; Heim, T.; Johnson, T. A.; Krizka, K.; Labitan, C.; Li, B.; Li, C.; MacFadyen, R.; Mladina, E.; Ottino, G.; Sanethavong, P.; Santpur, S. Neha; Witharm, R.] Lawrence Berkeley Natl Lab, Cyclotron Rd, Berkeley, CA 94720 USA, Email: APoley@cern.ch |
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Publisher  |
Iop Publishing Ltd |
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English |
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ISSN |
1748-0221 |
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Conference |
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Notes |
WOS:000577273400004 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
4572 |
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Author |
ATLAS Collaboration (Aad, G. et al); Aparisi Pozo, J.A.; Bailey, A.J.; Cabrera Urban, S.; Cardillo, F.; Castillo Gimenez, V.; Costa, M.J.; Escobar, C.; Estrada Pastor, O.; Ferrer, A.; Fiorini, L.; Fullana Torregrosa, E.; Fuster, J.; Garcia, C.; Garcia Navarro, J.E.; Gonzalez de la Hoz, S.; Gonzalvo Rodriguez, G.R.; Guerrero Rojas, J.G.R.; Higon-Rodriguez, E.; Lacasta, C.; Lozano Bahilo, J.J.; Mamuzic, J.; Marti-Garcia, S.; Martinez Agullo, P.; Mitsou, V.A.; Moreno Llacer, M.; Navarro-Gonzalez, J.; Poveda, J.; Prades Ibañez, A.; Ruiz-Martinez, A.; Sabatini, P.; Salt, J.; Sayago Galvan, I.; Soldevila, U.; Sanchez, J.; Torro Pastor, E.; Valero, A.; Valls Ferrer, J.A.; Villaplana Perez, M.; Vos, M. |
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Title |
The ATLAS Fast TracKer system |
Type |
Journal Article |
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Year |
2021 |
Publication |
Journal of Instrumentation |
Abbreviated Journal |
J. Instrum. |
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Volume |
16 |
Issue |
7 |
Pages |
P07006 - 61pp |
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Keywords |
Modular electronics; Online farms and online filtering; Pattern recognition, cluster finding, calibration and fitting methods; Trigger concepts and systems (hardware and software) |
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Abstract |
The ATLAS Fast TracKer (FTK) was designed to provide full tracking for the ATLAS high-level trigger by using pattern recognition based on Associative Memory (AM) chips and fitting in high-speed field programmable gate arrays. The tracks found by the FTK are based on inputs from all modules of the pixel and silicon microstrip trackers. The as-built FTK system and components are described, as is the online software used to control them while running in the ATLAS data acquisition system. Also described is the simulation of the FTK hardware and the optimization of the AM pattern banks. An optimization for long-lived particles with large impact parameter values is included. A test of the FTK system with the data playback facility that allowed the FTK to be commissioned during the shutdown between Run 2 and Run 3 of the LHC is reported. The resulting tracks from part of the FTK system covering a limited eta-phi region of the detector are compared with the output from the FTK simulation. It is shown that FTK performance is in good agreement with the simulation. |
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Address |
[Duvnjak, D.; Jackson, P.; Kong, A. X. Y.; Oliver, J. L.; Ruggeri, T. A.; Sharma, A. S.; White, M. J.] Univ Adelaide, Dept Phys, Adelaide, SA, Australia |
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IOP Publishing Ltd |
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English |
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ISSN |
1748-0221 |
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Conference |
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Notes |
WOS:000791152800006 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
5225 |
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Author |
Belver, D.; Cabanelas, P.; Castro, E.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. |
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Title |
Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall |
Type |
Journal Article |
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Year |
2010 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
57 |
Issue |
5 |
Pages |
2848-2856 |
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Keywords |
Charge to width algorithm; fast amplifying and digitizing electronics; front-end electronics; HADES; time of flight; timing RPC |
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Abstract |
A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m(2) divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel Daughter BOard(DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade [1]. The commissioning of the whole RPC wall is finished and the 6 sectors are already mounted in their final position in the HADES spectrometer and ready to take data during the beam-times foreseen for 2010. |
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Address |
[Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.] Univ Santiago Compostela, LabCAF, Santiago De Compostela 15782, Spain, Email: daniel.belver@usc.es |
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Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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ISSN |
0018-9499 |
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Notes |
ISI:000283440400007 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ elepoucu @ |
Serial |
349 |
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Author |
Carrio, F.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Higon-Rodriguez, E.; Marin, C.; Moreno, P.; Sanchis, E.; Solans, C.; Valero, A.; Valls Ferrer, J.A. |
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Title |
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment |
Type |
Journal Article |
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Year |
2011 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
58 |
Issue |
4 |
Pages |
1657-1663 |
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Keywords |
High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices |
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Abstract |
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol. |
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Address |
[Carrio, F; Gonzalez, V; Marin, C; Sanchis, E] Univ Valencia, Dept Elect Engn, E-46100 Valencia, Spain, Email: vicente.gonzalez@uv.es |
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Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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0018-9499 |
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Notes |
WOS:000293975700037 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
no |
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Call Number |
IFIC @ elepoucu @ |
Serial |
722 |
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Author |
Egea Canet, F.J. et al; Gadea, A.; Huyuk, T. |
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Title |
A New Front-End High-Resolution Sampling Board for the New-Generation Electronics of EXOGAM2 and NEDA Detectors |
Type |
Journal Article |
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Year |
2015 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
62 |
Issue |
3 |
Pages |
1056-1062 |
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Keywords |
Acquisition in HP-Ge detectors; high-speed ADCs; low-noise electronics design |
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Abstract |
This paper presents the final design and results of the FADC Mezzanine for the EXOGAM (EXOtic GAMma array spectrometer) and NEDA (Neutron Detector Array) detectors. The measurements performed include those of studying the effective number of bits, the energy resolution using HP-Ge detectors, as well as timing histograms and discrimination performance. Finally, the conclusion shows how a common digitizing device has been integrated in the experimental environment of two very different detectors which combine both low-noise acquisition and fast sampling rates. Not only the integration fulfilled the expected specifications on both systems, but it also showed how a study of synergy between detectors could lead to the reduction of resources and time by applying a common strategy. |
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Address |
[Egea Canet, F. J.; Gonzalez, V.; Sanchis, E.] Univ Valencia, Dept Elect Engn, Escola Tecn Super Engn, Valencia, Spain, Email: jaegea@ific.uv.es |
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Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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ISSN |
0018-9499 |
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Notes |
WOS:000356458000028 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
2278 |
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| Permanent link to this record |
