ATLAS Collaboration(Aad, G. et al), Cabrera Urban, S., Castillo Gimenez, V., Costa, M. J., Fassi, F., Ferrer, A., et al. (2014). Standalone vertex finding in the ATLAS muon spectrometer. J. Instrum., 9, P02001–39pp.
Abstract: A dedicated reconstruction algorithm to find decay vertices in the ATLAS muon spectrometer is presented. The algorithm searches the region just upstream of or inside the muon spectrometer volume for multi-particle vertices that originate from the decay of particles with long decay paths. The performance of the algorithm is evaluated using both a sample of simulated Higgs boson events, in which the Higgs boson decays to long-lived neutral particles that in turn decay to b (b) over bar final states, and pp collision data at root s = 7 TeV collected with the ATLAS detector at the LHC during 2011.
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Gonzalez-Sevilla, S. et al, Bernabeu Verdu, J., Civera, J. V., Garcia, C., Lacasta, C., Marco, R., et al. (2014). A double-sided silicon micro-strip Super-Module for the ATLAS Inner Detector upgrade in the High-Luminosity LHC. J. Instrum., 9, P02003–37pp.
Abstract: The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several years of successful data-taking, the LHC physics programme will be extended in the so-called High-Luminosity LHC, where the instantaneous luminosity will be increased up to 5 x 10(34) cm(-2) s(-1). For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as the existing detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip detectors at intermediate and outer radii. The super-module is an integration concept proposed for the strip region of the future ATLAS tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local support structure. An electrical super-module prototype for eight double-sided strip modules has been constructed. The aim is to exercise the multi-module readout chain and to investigate the noise performance of such a system. In this paper, the main components of the current super-module prototype are described and its electrical performance is presented in detail.
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Ros, A., Lerche, C. W., Sebastia, A., Sanchez, F., & Benlloch, J. M. (2014). Retroreflector arrays for better light collection efficiency of gamma-ray imaging detectors with continuous scintillation crystals without DOI misestimation. J. Instrum., 9, P04009–14pp.
Abstract: A method to improve light collection efficiency of gamma-ray imaging detectors by using retroreflector arrays has been tested, simulations of the behaviour of the scintillation light illuminating the retroreflector surface have been made. Measurements including retroreflector arrays in the setup have also been taken. For the measurements, positron emission tomography (PET) detectors with continuous scintillation crystals have been used. Each detector module consists of a continuous LSO-scintillator of dimensions 49x49x10 mm(3) and a H8500 position-sensitive photo-multiplier (PSPMT) from Hamamatsu. By using a continuous scintillation crystal, the scintillation light distribution has not been destroyed and the energy, the centroids along the x- and y-direction and the depth of interaction (DOI) can be estimated. Simulations have also been run taking into account the use of continuous scintillation crystals. Due to the geometry of the continuous scintillation crystals in comparison with pixelated crystals, a good light collection efficiency is necessary to correctly reconstruct the impact point of the gamma-ray. The aim of this study is to investigate whether micro-machine retro-reflectors improve light yield without misestimation of the impact point. The results shows an improvement on the energy and centroid resolutions without worsening the depth of interaction resolution. Therefore it can be concluded that using retroreflector arrays at the entrance side of the scintillation crystal improves light collection efficiency without worsening the impact point estimation.
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NEXT Collaboration(Alvarez, V. et al), Carcel, S., Cervera-Villanueva, A., Diaz, J., Ferrario, P., Gil, A., et al. (2014). Description and commissioning of NEXT-MM prototype: first results from operation in a Xenon-Trimethylamine gas mixture. J. Instrum., 9, P03010–22pp.
Abstract: A technical description of NEXT-MM and its commissioning and first performance is reported. Having an active volume of similar to 35 cm drift x 28 cm diameter, it constitutes the largest Micromegas-read TPC operated in Xenon ever constructed, made by a sectorial arrangement of the 4 largest single wafers manufactured with the Microbulk technique to date. It is equipped with a suitably pixelized readout and with a sufficiently large sensitive volume (similar to 23 l) so as to contain long (similar to 20 cm) electron tracks. First results obtained at 1 bar for Xenon and Trymethylamine (Xe-(2%) TMA) mixture are presented. The TPC can accurately reconstruct extended background tracks. An encouraging full-width half-maximum of 11.6% was obtained for similar to 29 keV gammas without resorting to any data post-processing.
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Carrio, F., Kim, H. Y., Moreno, P., Reed, R., Sandrock, C., Schettino, V., et al. (2014). Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench. J. Instrum., 9, C03023–12pp.
Abstract: The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception.
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