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Author Belver, D.; Cabanelas, P.; Castro, E.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. doi  openurl
  Title Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall Type Journal Article
  Year 2010 Publication (up) IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 57 Issue 5 Pages 2848-2856  
  Keywords Charge to width algorithm; fast amplifying and digitizing electronics; front-end electronics; HADES; time of flight; timing RPC  
  Abstract A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m(2) divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel Daughter BOard(DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade [1]. The commissioning of the whole RPC wall is finished and the 6 sectors are already mounted in their final position in the HADES spectrometer and ready to take data during the beam-times foreseen for 2010.  
  Address [Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.] Univ Santiago Compostela, LabCAF, Santiago De Compostela 15782, Spain, Email: daniel.belver@usc.es  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes ISI:000283440400007 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ elepoucu @ Serial 349  
Permanent link to this record
 

 
Author Egea Canet, F.J. et al; Gadea, A.; Huyuk, T. doi  openurl
  Title Digital Front-End Electronics for the Neutron Detector NEDA Type Journal Article
  Year 2015 Publication (up) IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 62 Issue 3 Pages 1063-1069  
  Keywords Digital systems; front-end electronics; neutron detectors; neutron-gamma discrimination  
  Abstract This paper presents the design of the NEDA (Neutron Detector Array) electronics, a first attempt to involve the use of digital electronics in large neutron detector arrays. Starting from the front-end modules attached to the PMTs (PhotoMultiplier Tubes) and ending up with the data processing workstations, a comprehensive electronic system capable of dealing with the acquisition and pre-processing of the neutron array is detailed. Among the electronic modules required, we emphasize the front-end analog processing, the digitalization, digital pre-processing and communications firmware, as well as the integration of the GTS (Global Trigger and Synchronization) system, already used successfully in AGATA (Advanced Gamma Tracking Array). The NEDA array will be available for measurements in 2016.  
  Address [Egea Canet, F. J.; Gonzalez, V.; Sanchis, E.] Univ Valencia, Dept Elect Engn, Escola Tecn Super Engn, Valencia, Spain, Email: jaegea@ific.uv.es  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000356458000029 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ pastor @ Serial 2279  
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Author Barrientos, D.; Bellato, M.; Bazzacco, D.; Bortolato, D.; Cocconi, P.; Gadea, A.; Gonzalez, V.; Gulmini, M.; Isocrate, R.; Mengoni, D.; Pullia, A.; Recchia, F.; Rosso, D.; Sanchis, E.; Toniolo, N.; Ur, C.A.; Valiente-Dobon, J.J. url  doi
openurl 
  Title Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array Type Journal Article
  Year 2015 Publication (up) IEEE Transactions on Nuclear Science Abbreviated Journal IEEE Trans. Nucl. Sci.  
  Volume 62 Issue 6 Pages 3134-3139  
  Keywords FPGA; front-end electronics; gamma-ray spectroscopy; germanium detectors  
  Abstract In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.53% at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs.  
  Address [Barrientos, D.; Bortolato, D.; Cocconi, P.; Gulmini, M.; Rosso, D.; Toniolo, N.; Valiente-Dobon, J. J.] Ist Nazl Fis Nucl, Lab Nazl Legnaro, I-35020 Padua, Italy, Email: diego.barrientos@lnl.infn.it  
  Corporate Author Thesis  
  Publisher Ieee-Inst Electrical Electronics Engineers Inc Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 0018-9499 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000372013500005 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ pastor @ Serial 2612  
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Author KM3NeT Collaboration (Aiello, S. et al); Calvo, D.; Coleiro, A.; Colomer, M.; Gozzini, S.R.; Hernandez-Rey, J.J.; Illuminati, G.; Khan Chowdhury, N.R.; Manczak, J.; Pieterse, C.; Real, D.; Thakore, T.; Zornoza, J.D.; Zuñiga, J. url  doi
openurl 
  Title KM3NeT front-end and readout electronics system: hardware, firmware, and software Type Journal Article
  Year 2019 Publication (up) Journal of Astronomical Telescopes, Instruments and Systems Abbreviated Journal J. Astron. Telesc. Instrum. Syst.  
  Volume 5 Issue 4 Pages 046001 - 15pp  
  Keywords front-end electronics; readout electronics; neutrino telescope; KM3NeT  
  Abstract The KM3NeT research infrastructure being built at the bottom of the Mediterranean Sea will host water-Cherenkov telescopes for the detection of cosmic neutrinos. The neutrino telescopes will consist of large volume three-dimensional grids of optical modules to detect the Cherenkov light from charged particles produced by neutrino-induced interactions. Each optical module houses 31 3-in. photomultiplier tubes, instrumentation for calibration of the photomultiplier signal and positioning of the optical module, and all associated electronics boards. By design, the total electrical power consumption of an optical module has been capped at seven Watts. We present an overview of the front-end and readout electronics system inside the optical module, which has been designed for a 1-ns synchronization between the clocks of all optical modules in the grid during a life time of at least 20 years. (C) 2019 Society of Photo-Optical Instrumentation Engineers (SPIE)  
  Address [Aiello, Sebastiano; Leonora, Emanuele; Longhitano, Fabio; Randazzo, Nunzio] INFN, Sez Catania, Catania, Italy, Email: v.van.beveren@nikhef.nl;  
  Corporate Author Thesis  
  Publisher Spie-Soc Photo-Optical Instrumentation Engineers Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 2329-4124 ISBN Medium  
  Area Expedition Conference  
  Notes WOS:000510649500024 Approved no  
  Is ISI yes International Collaboration yes  
  Call Number IFIC @ pastor @ Serial 4282  
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Author Marco-Hernandez, R. doi  openurl
  Title Development of a beam test telescope based on the Alibava readout system Type Journal Article
  Year 2011 Publication (up) Journal of Instrumentation Abbreviated Journal J. Instrum.  
  Volume 6 Issue Pages C01002 - 7pp  
  Keywords Particle tracking detectors; Data acquisition circuits; Front-end electronics for detector readout; Digital electronic circuits  
  Abstract A telescope for a beam test have been developed as a result of a collaboration among the University of Liverpool, Centro Nacional de Microelectronica (CNM) of Barcelona and Instituto de Fisica Corpuscular (IFIC) of Valencia. This system is intended to carry out both analogue charge collection and spatial resolution measurements with different types of microstrip or pixel silicon detectors in a beam test environment. The telescope has four XY measurement as well as trigger planes (XYT board) and it can accommodate up to twelve devices under test (DUT board). The DUT board uses two Beetle ASICs for the readout of chilled silicon detectors. The board could operate in a self-triggering mode. The board features a temperature sensor and it can be mounted on a rotary stage. A peltier element is used for cooling the DUT. Each XYT board measures the track space points using two silicon strip detectors connected to two Beetle ASICs. It can also trigger on the particle tracks in the beam test. The board includes a CPLD which allows for the synchronization of the trigger signal to a common clock frequency, delaying and implementing coincidence with other XYT boards. An Alibava mother board is used to read out and to control each XYT/DUT board from a common trigger signal and a common clock signal. The Alibava board has a TDC on board to have a time stamp of each trigger. The data collected by each Alibava board is sent to a master card by means of a local data/address bus following a custom digital protocol. The master board distributes the trigger, clock and reset signals. It also merges the data streams from up to sixteen Alibava boards. The board has also a test channel for testing in a standard mode a XYT or DUT board. This board is implemented with a Xilinx development board and a custom patch board. The master board is connected with the DAQ software via 100M Ethernet. Track based alignment software has also been developed for the data obtained with the DAQ software.  
  Address [Marco-Hernandez, R.; Alibava Collaboration] CSIC UV, Inst Fis Corpuscular, E-46980 Paterna, Valencia, Spain, Email: rmarco@ific.uv.es  
  Corporate Author Thesis  
  Publisher Iop Publishing Ltd Place of Publication Editor  
  Language English Summary Language Original Title  
  Series Editor Series Title Abbreviated Series Title  
  Series Volume Series Issue Edition  
  ISSN 1748-0221 ISBN Medium  
  Area Expedition Conference  
  Notes ISI:000291345600007 Approved no  
  Is ISI yes International Collaboration no  
  Call Number IFIC @ elepoucu @ Serial 644  
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