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Author |
Aliaga, R.J.; Herrero-Bosch, V.; Capra, S.; Pullia, A.; Duenas, J.A.; Grassi, L.; Triossi, A.; Domingo-Pardo, C.; Gadea, R.; Gonzalez, V.; Huyuk, T.; Sanchis, E.; Gadea, A.; Mengoni, D. |
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Title |
Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC |
Type |
Journal Article |
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Year |
2015 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
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Volume |
800 |
Issue |
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Pages |
34-39 |
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Keywords  |
Analog memory; Dead time; Detector readout; Front-end electronics; Switched Capacitor Array (SCA); Triggerless data acquisition |
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Abstract |
The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling, Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations. |
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Address |
[Aliaga, R. J.; Domingo-Pardo, C.; Hueyuek, T.; Gadea, A.] Inst Fis Corpuscular, Paterna 46980, Spain, Email: raalva@ific.uv.es |
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Elsevier Science Bv |
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English |
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ISSN |
0168-9002 |
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Conference |
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Notes |
WOS:000361878200006 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
2407 |
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Author |
Alvarez, V.; Herrero-Bosch, V.; Esteve, R.; Laing, A.; Rodriguez, J.; Querol, M.; Monrabal, F.; Toledo, J.F.; Gomez-Cadenas, J.J. |
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Title |
The electronics of the energy plane of the NEXT-White detector |
Type |
Journal Article |
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Year |
2019 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
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Volume |
917 |
Issue |
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Pages |
68-76 |
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Keywords |
Calorimetry; Front-end electronics; Digital baseline restoration |
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Abstract |
This paper describes the electronics of NEXT-White (NEW) detector PMT plane, a high pressure xenon TPC with electroluminescent amplification (HPXe-EL) currently operating at the Laboratorio Subterraneo de Canfranc (LSC) in Huesca, Spain. In NEXT-White the energy of the event is measured by a plane of photomultipliers (PMTs) located behind a transparent cathode. The PMTs are Hamamatsu R11410-10 chosen due to their low radioactivity. The electronics have been designed and implemented to fulfill strict requirements: an overall energy resolution below 1% and a radiopurity budget of 20 mBq unit(-1) in the chain of Bi-214. All the components and materials have been carefully screened to assure a low radioactivity level and at the same time meet the required front-end electronics specifications. In order to reduce low frequency noise effects and enhance detector safety a grounded cathode connection has been used for the PMTs. This implies an AC-coupled readout and baseline variations in the PMT signals. A detailed description of the electronics and a novel approach based on a digital baseline restoration to obtain a linear response and handle AC coupling effects is presented. The final PMT channel design has been characterized with linearity better than 0.4% and noise below 0.4 mV. |
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Address |
[Alvarez, V; Laing, A.; Rodriguez, J.; Querol, M.; Gomez-Cadenas, J. J.] CSIC, IFIC, Inst Fis Corpuscular, Calle Catedrat Jose Beltran 2, Valencia 46980, Spain, Email: vicente.alvarez@ific.uv.es |
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Elsevier Science Bv |
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English |
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ISSN |
0168-9002 |
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Expedition |
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Conference |
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Notes |
WOS:000455016500010 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
3868 |
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Author |
Belver, D.; Cabanelas, P.; Castro, E.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. |
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Title |
Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall |
Type |
Journal Article |
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Year |
2010 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
57 |
Issue |
5 |
Pages |
2848-2856 |
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Keywords |
Charge to width algorithm; fast amplifying and digitizing electronics; front-end electronics; HADES; time of flight; timing RPC |
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Abstract |
A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m(2) divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel Daughter BOard(DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade [1]. The commissioning of the whole RPC wall is finished and the 6 sectors are already mounted in their final position in the HADES spectrometer and ready to take data during the beam-times foreseen for 2010. |
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Address |
[Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.] Univ Santiago Compostela, LabCAF, Santiago De Compostela 15782, Spain, Email: daniel.belver@usc.es |
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Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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ISSN |
0018-9499 |
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Notes |
ISI:000283440400007 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ elepoucu @ |
Serial |
349 |
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Author |
Poley, L. et al; Bernabeu, J.; Civera, J.V.; Lacasta, C.; Leon, P.; Platero, A.; Platero, V; Solaz, C.; Soldevila, U.; Vidal, G. |
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Title |
The ABC130 barrel module prototyping programme for the ATLAS strip tracker |
Type |
Journal Article |
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Year |
2020 |
Publication |
Journal of Instrumentation |
Abbreviated Journal |
J. Instrum. |
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Volume |
15 |
Issue |
9 |
Pages |
P09004 - 78pp |
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Keywords |
Detector design and construction technologies and materials; Si microstrip and pad detectors; Radiation-hard detectors; Front-end electronics for detector readout |
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Abstract |
For the Phase-II Upgrade of the ATLAS Detector [1], its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100% silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: an early program using readout chips designed using a 250 nm fabrication process (ABCN-250) [2, 3] and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests. |
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Address |
[Poley, L.; Anderssen, E.; Ciocio, A.; Cornell, E.; Haber, C.; Haugen, T. E.; Heim, T.; Johnson, T. A.; Krizka, K.; Labitan, C.; Li, B.; Li, C.; MacFadyen, R.; Mladina, E.; Ottino, G.; Sanethavong, P.; Santpur, S. Neha; Witharm, R.] Lawrence Berkeley Natl Lab, Cyclotron Rd, Berkeley, CA 94720 USA, Email: APoley@cern.ch |
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Publisher |
Iop Publishing Ltd |
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English |
Summary Language |
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ISSN |
1748-0221 |
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Notes |
WOS:000577273400004 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
4572 |
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Author |
Egea Canet, F.J. et al; Gadea, A.; Huyuk, T. |
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Title |
Digital Front-End Electronics for the Neutron Detector NEDA |
Type |
Journal Article |
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Year |
2015 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
62 |
Issue |
3 |
Pages |
1063-1069 |
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Keywords |
Digital systems; front-end electronics; neutron detectors; neutron-gamma discrimination |
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Abstract |
This paper presents the design of the NEDA (Neutron Detector Array) electronics, a first attempt to involve the use of digital electronics in large neutron detector arrays. Starting from the front-end modules attached to the PMTs (PhotoMultiplier Tubes) and ending up with the data processing workstations, a comprehensive electronic system capable of dealing with the acquisition and pre-processing of the neutron array is detailed. Among the electronic modules required, we emphasize the front-end analog processing, the digitalization, digital pre-processing and communications firmware, as well as the integration of the GTS (Global Trigger and Synchronization) system, already used successfully in AGATA (Advanced Gamma Tracking Array). The NEDA array will be available for measurements in 2016. |
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Address |
[Egea Canet, F. J.; Gonzalez, V.; Sanchis, E.] Univ Valencia, Dept Elect Engn, Escola Tecn Super Engn, Valencia, Spain, Email: jaegea@ific.uv.es |
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Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0018-9499 |
ISBN |
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Expedition |
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Conference |
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Notes |
WOS:000356458000029 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number |
IFIC @ pastor @ |
Serial |
2279 |
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| Permanent link to this record |
