| Records |
| Author |
Valero, A.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Hernandez Jimenez, Y.; Higon-Rodriguez, E.; Sanchis, E.; Solans, C.; Torres, J.; Valls Ferrer, J.A. |
| Title |
The ATLAS tile calorimeter ROD injector and multiplexer board |
Type |
Journal Article |
| Year |
2011 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
| Volume |
629 |
Issue |
1 |
Pages |
74-79 |
| Keywords |
LHC; ATLAS; Calorimeter; Data acquisition; FPGA; Bit error rate |
| Abstract |
The ATLAS Tile Calorimeter is a sampling detector composed by cells made of iron-scintillator tiles. The calorimeter cell signals are digitized in the front-end electronics and transmitted to the Read-Out Drivers (RODs) at the first level trigger rate. The ROD receives triggered data from up to 9856 channels and provides the energy, phase and quality factor of the signals to the second level trigger. The back-end electronics is divided into four partitions containing eight RODs each. Therefore, a total of 32 RODs are used to process and transmit the data of the TileCal detector. In order to emulate the detector signals in the production and commissioning of ROD modules a board called ROD Injector and Multiplexer Board (RIMBO) was designed. In this paper, the RIMBO main functional blocks, PCB design and the different operation modes are described. It is described the crucial role of the board within the TileCal ROD test-bench in order to emulate the front-end electronics during the validation of ROD boards as well as during the evaluation of the ROD signal reconstruction algorithms. Finally, qualification and performance results for the injection operation mode obtained during the Tile Calorimeter ROD production tests are presented. |
| Address |
[Valero, A.; Castillo, V.; Ferrer, A.; Hernandez, Y.; Higon, E.; Solans, C.; Valls, J. A.] Univ Valencia, CSIC, Inst Fis Corpuscular, Valencia 46071, Spain, Email: alberto.valero@cern.ch |
| Corporate Author |
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Thesis |
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| Publisher |
Elsevier Science Bv |
Place of Publication |
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Editor |
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| Language |
English |
Summary Language |
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Original Title |
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| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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ISSN  |
0168-9002 |
ISBN |
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Medium |
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| Area |
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Expedition |
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Conference |
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| Notes |
ISI:000287556100012 |
Approved |
no |
| Is ISI |
yes |
International Collaboration |
no |
| Call Number |
IFIC @ pastor @ |
Serial |
555 |
| Permanent link to this record |
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| Author |
Jaworski, G.; Palacz, M.; Nyberg, J.; de Angelis, G.; de France, G.; Di Nitto, A.; Egea, F.J.; Erduran, M.N.; Erturk, S.; Farnea, E.; Gadea, A.; Gonzalez, V.; Gottardo, A.; Huyuk, T.; Kownacki, J.; Pipidis, A.; Roeder, B.; Soderstrom, P.A.; Sanchis, E.; Tarnowski, R.; Triossi, A.; Wadsworth, R.; Valiente-Dobon, J.J. |
| Title |
Monte Carlo simulation of a single detector unit for the neutron detector array NEDA |
Type |
Journal Article |
| Year |
2012 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
| Volume |
673 |
Issue |
|
Pages |
64-72 |
| Keywords |
Monte Carlo simulation; BC501; BC501A; BC537; Liquid scintillator; Neutron detector; Geant4; NEDA |
| Abstract |
A study of the dimensions and performance of a single detector of the future neutron detector array NEDA was performed by means of Monte Carlo simulations, using GEANT4. Two different liquid scintillators were evaluated: the hydrogen based BC501A and the deuterated BC537. The efficiency and the probability that one neutron will trigger a signal in more than one detector were investigated as a function of the detector size. The simulations were validated comparing the results to experimental measurements performed with two existing neutron detectors, with different geometries, based on the liquid scintillator BC501. |
| Address |
[Jaworski, G.; Palacz, M.; Kownacki, J.; Tarnowski, R.] Univ Warsaw, Heavy Ion Lab, PL-02093 Warsaw, Poland, Email: palacz@slcj.uw.edu.pl |
| Corporate Author |
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Thesis |
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| Publisher |
Elsevier Science Bv |
Place of Publication |
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Editor |
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| Language |
English |
Summary Language |
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Original Title |
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| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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| ISSN |
0168-9002 |
ISBN |
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Medium |
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| Area |
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Expedition |
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Conference |
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| Notes |
WOS:000301813500009 |
Approved |
no |
| Is ISI |
yes |
International Collaboration |
yes |
| Call Number |
IFIC @ pastor @ |
Serial |
944 |
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| Author |
Modamio, V.; Valiente-Dobon, J.J.; Jaworski, G.; Huyuk, T.; Triossi, A.; Egea, J.; Di Nitto, A.; Soderstrom, P.A.; Ros, J.A.; de Angelis, G.; de France, G.; Erduran, M.N.; Erturk, S.; Gadea, A.; Gonzalez, V.; Kownacki, J.; Moszynski, M.; Nyberg, J.; Palacz, M.; Sanchis, E.; Wadsworthm, R. |
| Title |
Digital pulse-timing technique for the neutron detector array NEDA |
Type |
Journal Article |
| Year |
2015 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
| Volume |
775 |
Issue |
|
Pages |
71-76 |
| Keywords |
Digital timing; Constant fraction discriminator; Liquid scintillator; BC501A; Neutron detector; NEDA |
| Abstract |
A new digital pulse-timing algorithm, to be used with the future neutron detector array NEDA, has been developed and tested. The time resolution of four 5 in diameter photomultiplier tubes (XP4512, R4144, R11833-100, and ET9390-kb), coupled to a cylindrical 5 in by 5 in BC501A liquict scintillator detector was measured by employing digital sampling electronics and a constant fraction discriminator (CFD) algorithm. The zero crossing of the CM algorithm was obtained with a cubic spline interpolation, which was continuous up to the second derivative. The performance of the algorithm was studied at sampling rates of 500 MS/s and 200 MS/s. The time resolution obtained with the digital electronics was compared to the values acquired with a standard analog CFD. The result of this comparison shows that the time resolution from the analog and the digital measurements at 500 MS/s and at 200 MS/s are within 15% for all the tested photomultiplier tubes. |
| Address |
[Modamio, V.; Valiente-Dobon, J. J.; Triossi, A.; de Angelis, G.] Ist Nazl Fis Nucl, Lab Nazl Legnaro, I-35020 Legnaro, Italy, Email: victor.modamio@lnl.infn.it |
| Corporate Author |
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Thesis |
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| Publisher |
Elsevier Science Bv |
Place of Publication |
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Editor |
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| Language |
English |
Summary Language |
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Original Title |
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| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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| ISSN |
0168-9002 |
ISBN |
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Medium |
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| Area |
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Expedition |
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Conference |
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| Notes |
WOS:000348040900011 |
Approved |
no |
| Is ISI |
yes |
International Collaboration |
yes |
| Call Number |
IFIC @ pastor @ |
Serial |
2093 |
| Permanent link to this record |
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| Author |
Aliaga, R.J.; Herrero-Bosch, V.; Capra, S.; Pullia, A.; Duenas, J.A.; Grassi, L.; Triossi, A.; Domingo-Pardo, C.; Gadea, R.; Gonzalez, V.; Huyuk, T.; Sanchis, E.; Gadea, A.; Mengoni, D. |
| Title |
Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC |
Type |
Journal Article |
| Year |
2015 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
| Volume |
800 |
Issue |
|
Pages |
34-39 |
| Keywords |
Analog memory; Dead time; Detector readout; Front-end electronics; Switched Capacitor Array (SCA); Triggerless data acquisition |
| Abstract |
The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling, Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations. |
| Address |
[Aliaga, R. J.; Domingo-Pardo, C.; Hueyuek, T.; Gadea, A.] Inst Fis Corpuscular, Paterna 46980, Spain, Email: raalva@ific.uv.es |
| Corporate Author |
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Thesis |
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| Publisher |
Elsevier Science Bv |
Place of Publication |
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Editor |
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| Language |
English |
Summary Language |
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Original Title |
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| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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| ISSN |
0168-9002 |
ISBN |
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Medium |
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| Area |
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Expedition |
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Conference |
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| Notes |
WOS:000361878200006 |
Approved |
no |
| Is ISI |
yes |
International Collaboration |
yes |
| Call Number |
IFIC @ pastor @ |
Serial |
2407 |
| Permanent link to this record |
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| Author |
Carrio, F.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Higon-Rodriguez, E.; Marin, C.; Moreno, P.; Sanchis, E.; Solans, C.; Valero, A.; Valls Ferrer, J.A. |
| Title |
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment |
Type |
Journal Article |
| Year |
2011 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
| Volume |
58 |
Issue |
4 |
Pages |
1657-1663 |
| Keywords |
High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices |
| Abstract |
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol. |
| Address |
[Carrio, F; Gonzalez, V; Marin, C; Sanchis, E] Univ Valencia, Dept Elect Engn, E-46100 Valencia, Spain, Email: vicente.gonzalez@uv.es |
| Corporate Author |
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Thesis |
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| Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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| Language |
English |
Summary Language |
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Original Title |
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| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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| ISSN |
0018-9499 |
ISBN |
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Medium |
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| Area |
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Expedition |
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Conference |
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| Notes |
WOS:000293975700037 |
Approved |
no |
| Is ISI |
yes |
International Collaboration |
no |
| Call Number |
IFIC @ elepoucu @ |
Serial |
722 |
| Permanent link to this record |
