Records |
Author |
Valero, A.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Hernandez Jimenez, Y.; Higon-Rodriguez, E.; Sanchis, E.; Solans, C.; Torres, J.; Valls Ferrer, J.A. |
Title |
The ATLAS tile calorimeter ROD injector and multiplexer board |
Type |
Journal Article |
Year |
2011 |
Publication |
Nuclear Instruments & Methods in Physics Research A |
Abbreviated Journal |
Nucl. Instrum. Methods Phys. Res. A |
Volume |
629 |
Issue |
1 |
Pages |
74-79 |
Keywords |
LHC; ATLAS; Calorimeter; Data acquisition; FPGA; Bit error rate |
Abstract |
The ATLAS Tile Calorimeter is a sampling detector composed by cells made of iron-scintillator tiles. The calorimeter cell signals are digitized in the front-end electronics and transmitted to the Read-Out Drivers (RODs) at the first level trigger rate. The ROD receives triggered data from up to 9856 channels and provides the energy, phase and quality factor of the signals to the second level trigger. The back-end electronics is divided into four partitions containing eight RODs each. Therefore, a total of 32 RODs are used to process and transmit the data of the TileCal detector. In order to emulate the detector signals in the production and commissioning of ROD modules a board called ROD Injector and Multiplexer Board (RIMBO) was designed. In this paper, the RIMBO main functional blocks, PCB design and the different operation modes are described. It is described the crucial role of the board within the TileCal ROD test-bench in order to emulate the front-end electronics during the validation of ROD boards as well as during the evaluation of the ROD signal reconstruction algorithms. Finally, qualification and performance results for the injection operation mode obtained during the Tile Calorimeter ROD production tests are presented. |
Address |
[Valero, A.; Castillo, V.; Ferrer, A.; Hernandez, Y.; Higon, E.; Solans, C.; Valls, J. A.] Univ Valencia, CSIC, Inst Fis Corpuscular, Valencia 46071, Spain, Email: alberto.valero@cern.ch |
Corporate Author |
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Thesis |
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Publisher |
Elsevier Science Bv |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0168-9002 |
ISBN |
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Medium |
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Area |
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Expedition |
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Conference |
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Notes |
ISI:000287556100012 |
Approved |
no |
Is ISI |
yes |
International Collaboration |
no |
Call Number |
IFIC @ pastor @ |
Serial |
555 |
Permanent link to this record |
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Author |
Carrio, F.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Higon-Rodriguez, E.; Marin, C.; Moreno, P.; Sanchis, E.; Solans, C.; Valero, A.; Valls Ferrer, J.A. |
Title |
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment |
Type |
Journal Article |
Year |
2011 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
Volume |
58 |
Issue |
4 |
Pages |
1657-1663 |
Keywords |
High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices |
Abstract |
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol. |
Address |
[Carrio, F; Gonzalez, V; Marin, C; Sanchis, E] Univ Valencia, Dept Elect Engn, E-46100 Valencia, Spain, Email: vicente.gonzalez@uv.es |
Corporate Author |
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Thesis |
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Publisher |
Ieee-Inst Electrical Electronics Engineers Inc |
Place of Publication |
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Editor |
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Language |
English |
Summary Language |
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Original Title |
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Series Editor |
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Series Title |
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Abbreviated Series Title |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
0018-9499 |
ISBN |
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Medium |
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Area |
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Expedition |
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Conference |
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Notes |
WOS:000293975700037 |
Approved |
no |
Is ISI |
yes |
International Collaboration |
no |
Call Number |
IFIC @ elepoucu @ |
Serial |
722 |
Permanent link to this record |