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Barrientos, D., Gonzalez, V., Bellato, M., Gadea, A., Bazzacco, D., Blasco, J. M., et al. (2013). Multiple Register Synchronization With a High-Speed Serial Link Using the Aurora Protocol. IEEE Trans. Nucl. Sci., 60(5), 3521–3525.
Abstract: In this work, the development and characterization of a multiple synchronous registers interface communicating with a high-speed serial link and using the Aurora protocol is presented. A detailed description of the developing process and the characterization methods and hardware test benches are also included. This interface will implement the slow control buses of the digitizer cards for the second generation of electronics for the Advanced GAmma Tracking Array (AGATA).
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Barrientos, D., Bellato, M., Bazzacco, D., Bortolato, D., Cocconi, P., Gadea, A., et al. (2015). Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array. IEEE Trans. Nucl. Sci., 62(6), 3134–3139.
Abstract: In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.53% at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs.
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Mengoni, D., Duenas, J. A., Assie, M., Boiano, C., John, P. R., Aliaga, R. J., et al. (2014). Digital pulse-shape analysis with a TRACE early silicon prototype. Nucl. Instrum. Methods Phys. Res. A, 764, 241–246.
Abstract: A highly segmented silicon-pad detector prototype has been tested to explore the performance of the digital pulse shape analysis in the discrimination of the particles reaching the silicon detector. For the first time a 200 tun thin silicon detector, grown using an ordinary floating zone technique, has been shown to exhibit a level discrimination thanks to the fine segmentation. Light-charged particles down to few MeV have been separated, including their punch-through. A coaxial HPGe detector in time coincidence has further confirmed the quality of the particle discrimination.
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Capra, S., Mengoni, D., Dueñas, J. A., John, P. R., Gadea, A., Aliaga, R. J., et al. (2019). Performance of the new integrated front-end electronics of the TRACE array commissioned with an early silicon detector prototype. Nucl. Instrum. Methods Phys. Res. A, 935, 178–184.
Abstract: The spectroscopic performances of the new integrated ASIC (Application-Specific Integrated Circuit) preamplifiers for highly segmented silicon detectors have been evaluated with an early silicon detector prototype of the TRacking Array for light Charged Ejectiles (TRACE). The ASICS were mounted on a custom-designed PCB (Printed Circuit Board) and the detector plugged on it. Energy resolution tests, performed on the same detector before and after irradiation, yielded a resolution of 21 keV and 33 keV FWHM respectively. The output signals were acquired with an array of commercial 100-MHz 14-bit digitizers. The preamplifier chip is equipped with an innovative Fast-Reset device that has two functions: it reduces dramatically the dead time of the preamplifier in case of saturation (from milliseconds to microseconds) and extends the spectroscopic dynamic range of the preamplifier by more than one order of magnitude. Other key points of the device are the low noise and the wide bandwidth.
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Aliaga, R. J., Herrero-Bosch, V., Capra, S., Pullia, A., Duenas, J. A., Grassi, L., et al. (2015). Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC. Nucl. Instrum. Methods Phys. Res. A, 800, 34–39.
Abstract: The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling, Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.
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