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Author |
Real, D.; Calvo, D.; Diaz, A.; Alves Garre, S.; Carretero, V.; Sanchez Losa, A.; Salesa Greus, F. |
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Title |
An Ultra-Narrow Time Optical Pulse Emitter Based on a Laser: UNTOPEL |
Type |
Journal Article |
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Year |
2023 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
70 |
Issue |
10 |
Pages |
2364-2372 |
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Keywords |
Instrumentation electronics; neutrino telescope instrumentation; subnanosecond light source; time calibration instrument |
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Abstract |
Light sources that emit repetitive subnanosecond pulses are used in neutrino telescopes for time calibration. Optical pulses with an ultra-narrow (subnanosecond) width can replicate the light produced by neutrino interactions, and are an important calibration and test element. By measuring the time-of-flight of the light, it is possible to provide a relative time calibration for all the detector photomultipliers. This work presents the ultra-narrow time optical pulse emitter based on a laser (UNTOPEL), an instrument emitting ultra-short laser optical pulses with a duration of 500 ps, energies per pulse of four microjoules at a wavelength of 532 nm, and a timing precision of 400 ps. The UNTOPEL pulse intensity can be fine-tuned, which is a novelty and a significant advantage in those applications that need to illuminate light detectors located at different distances with the same light intensity. The UNTOPEL pulse intensity can be controlled remotely, allowing for its use in operating conditions where physical access is impossible or difficult. Moreover, it is easy to operate and can be easily controlled through an inter-integrated circuit bus. The UNTOPEL is a sound instrument used when subnanosecond pulses and variable energy emissions are needed. |
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Address |
[Real, Diego; Calvo, David; Garre, Sergio Alves; Carretero, Victor; Losa, Agustin Sanchez; Greus, FranciscoSalesa] Univ Valencia, IFIC Inst Fis Corpuscular, CSIC, Paterna 46980, Spain, Email: real@ific.uv.es |
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Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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0018-9499 |
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WOS:001098078200010 |
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no |
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Is ISI |
yes |
International Collaboration |
no |
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Call Number ![sorted by Call Number field, descending order (down)](img/sort_desc.gif) |
IFIC @ pastor @ |
Serial |
5795 |
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Author |
Belver, D.; Cabanelas, P.; Castro, E.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. |
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Title |
Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall |
Type |
Journal Article |
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Year |
2010 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
57 |
Issue |
5 |
Pages |
2848-2856 |
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Keywords |
Charge to width algorithm; fast amplifying and digitizing electronics; front-end electronics; HADES; time of flight; timing RPC |
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Abstract |
A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m(2) divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel Daughter BOard(DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade [1]. The commissioning of the whole RPC wall is finished and the 6 sectors are already mounted in their final position in the HADES spectrometer and ready to take data during the beam-times foreseen for 2010. |
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[Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.] Univ Santiago Compostela, LabCAF, Santiago De Compostela 15782, Spain, Email: daniel.belver@usc.es |
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Ieee-Inst Electrical Electronics Engineers Inc |
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0018-9499 |
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Notes |
ISI:000283440400007 |
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no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number ![sorted by Call Number field, descending order (down)](img/sort_desc.gif) |
IFIC @ elepoucu @ |
Serial |
349 |
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Permanent link to this record |
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Author |
Tetrault, M.A.; Oliver, J.F.; Bergeron, M.; Lecomte, R.; Fontaine, R. |
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Title |
Real Time Coincidence Detection Engine for High Count Rate Timestamp Based PET |
Type |
Journal Article |
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Year |
2010 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
57 |
Issue |
1 |
Pages |
117-124 |
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Keywords |
Coincidence detection; Positron Emission Tomography (PET) |
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Abstract |
Coincidence engines follow two main implementation flows: timestamp based systems and AND-gate based systems. The latter have been more widespread in recent years because of its lower cost and high efficiency. However, they are highly dependent on the selected electronic components, they have limited flexibility once assembled and they are customized to fit a specific scanner's geometry. Timestamp based systems are gathering more attention lately, especially with high channel count fully digital systems. These new systems must however cope with important singles count rates. One option is to record every detected event and postpone coincidence detection offline. For daily use systems, a real time engine is preferable because it dramatically reduces data volume and hence image preprocessing time and raw data management. This paper presents the timestamp based coincidence engine for the LabPET(TM), a small animal PET scanner with up to 4608 individual readout avalanche photodiode channels. The engine can handle up to 100 million single events per second and has extensive flexibility because it resides in programmable logic devices. It can be adapted for any detector geometry or channel count, can be ported to newer, faster programmable devices and can have extra modules added to take advantage of scanner-specific features. Finally, the user can select between full processing mode for imaging protocols and minimum processing mode to study different approaches for coincidence detection with offline software. |
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[Tetrault, M. -A.; Fontaine, R.] Univ Sherbrooke, Dept Elect & Comp Engn, Sherbrooke, PQ J1K 2R1, Canada, Email: Marc-Andre.Tetrault@USherbrooke.ca |
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Ieee-Inst Electrical Electronics Engineers Inc |
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0018-9499 |
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Notes |
ISI:000274391000016 |
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no |
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Is ISI |
yes |
International Collaboration |
yes |
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Call Number ![sorted by Call Number field, descending order (down)](img/sort_desc.gif) |
IFIC @ elepoucu @ |
Serial |
500 |
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Permanent link to this record |
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Author |
Carrio, F.; Castillo Gimenez, V.; Ferrer, A.; Gonzalez, V.; Higon-Rodriguez, E.; Marin, C.; Moreno, P.; Sanchis, E.; Solans, C.; Valero, A.; Valls Ferrer, J.A. |
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Title |
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment |
Type |
Journal Article |
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Year |
2011 |
Publication |
IEEE Transactions on Nuclear Science |
Abbreviated Journal |
IEEE Trans. Nucl. Sci. |
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Volume |
58 |
Issue |
4 |
Pages |
1657-1663 |
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Keywords |
High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices |
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Abstract |
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol. |
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Address |
[Carrio, F; Gonzalez, V; Marin, C; Sanchis, E] Univ Valencia, Dept Elect Engn, E-46100 Valencia, Spain, Email: vicente.gonzalez@uv.es |
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Ieee-Inst Electrical Electronics Engineers Inc |
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English |
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0018-9499 |
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Notes |
WOS:000293975700037 |
Approved |
no |
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Is ISI |
yes |
International Collaboration |
no |
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Call Number ![sorted by Call Number field, descending order (down)](img/sort_desc.gif) |
IFIC @ elepoucu @ |
Serial |
722 |
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Permanent link to this record |