Belver, D., Cabanelas, P., Castro, E., Garzon, J. A., Gil, A., Gonzalez-Diaz, D., et al. (2010). Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall. IEEE Trans. Nucl. Sci., 57(5), 2848–2856.
Abstract: A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m(2) divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel Daughter BOard(DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade [1]. The commissioning of the whole RPC wall is finished and the 6 sectors are already mounted in their final position in the HADES spectrometer and ready to take data during the beam-times foreseen for 2010.
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Marco-Hernandez, R. (2011). Development of a beam test telescope based on the Alibava readout system. J. Instrum., 6, C01002–7pp.
Abstract: A telescope for a beam test have been developed as a result of a collaboration among the University of Liverpool, Centro Nacional de Microelectronica (CNM) of Barcelona and Instituto de Fisica Corpuscular (IFIC) of Valencia. This system is intended to carry out both analogue charge collection and spatial resolution measurements with different types of microstrip or pixel silicon detectors in a beam test environment. The telescope has four XY measurement as well as trigger planes (XYT board) and it can accommodate up to twelve devices under test (DUT board). The DUT board uses two Beetle ASICs for the readout of chilled silicon detectors. The board could operate in a self-triggering mode. The board features a temperature sensor and it can be mounted on a rotary stage. A peltier element is used for cooling the DUT. Each XYT board measures the track space points using two silicon strip detectors connected to two Beetle ASICs. It can also trigger on the particle tracks in the beam test. The board includes a CPLD which allows for the synchronization of the trigger signal to a common clock frequency, delaying and implementing coincidence with other XYT boards. An Alibava mother board is used to read out and to control each XYT/DUT board from a common trigger signal and a common clock signal. The Alibava board has a TDC on board to have a time stamp of each trigger. The data collected by each Alibava board is sent to a master card by means of a local data/address bus following a custom digital protocol. The master board distributes the trigger, clock and reset signals. It also merges the data streams from up to sixteen Alibava boards. The board has also a test channel for testing in a standard mode a XYT or DUT board. This board is implemented with a Xilinx development board and a custom patch board. The master board is connected with the DAQ software via 100M Ethernet. Track based alignment software has also been developed for the data obtained with the DAQ software.
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ANTARES Collaboration(Aguilar, J. A. et al), Bigongiari, C., Dornic, D., Emanuele, U., Gomez-Gonzalez, J. P., Hernandez-Rey, J. J., et al. (2010). Performance of the front-end electronics of the ANTARES neutrino telescope. Nucl. Instrum. Methods Phys. Res. A, 622(1), 59–73.
Abstract: ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip: results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.
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Barrio, J., Etxebeste, A., Lacasta, C., Muñoz, E., Oliver, J. F., Solaz, C., et al. (2015). Performance of VATA64HDR16 ASIC for medical physics applications based on continuous crystals and SiPMs. J. Instrum., 10, P12001–12pp.
Abstract: Detectors based on Silicon Photomultipliers (SiPMs) coupled to continuous crystals are being tested in medical physics applications due to their potential high resolution and sensitivity. To cope with the high granularity required for a very good spatial resolution, SiPM matrices with a large amount of elements are needed. To be able to read the information coming from each individual channel, dedicated ASICs are employed. The VATA64HDR16 ASIC is a 64-channel, charge-sensitive amplifier that converts the collected charge into a proportional current or voltage signal. A complete assessment of the suitability of that ASIC for medical physics applications based on continuous crystals and SiPMs has been carried out. The input charge range is linear from 20 pC up to 55 pC. The energy resolution obtained at 511 keV is 10% FWHM with a LaBr3 crystal and 16% FWHM with a LYSO crystal. A coincidence timing resolution of 24 ns FWHM is obtained with two LYSO crystals.
Keywords: Solid state detectors; Photon detectors for UV, visible and IR photons (solid-state) (PIN diodes, APDs, Si-PMTs, G-APDs, CCDs, EBCCDs, EMCCDs etc); Front-end electronics for detector readout; Gamma detectors (scintillators, CZT, HPG, HgI etc)
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Poley, L. et al, Bernabeu, J., Civera, J. V., Lacasta, C., Leon, P., Platero, A., et al. (2020). The ABC130 barrel module prototyping programme for the ATLAS strip tracker. J. Instrum., 15(9), P09004–78pp.
Abstract: For the Phase-II Upgrade of the ATLAS Detector [1], its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100% silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: an early program using readout chips designed using a 250 nm fabrication process (ABCN-250) [2, 3] and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests.
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