@Article{Aliaga_etal2015,
author="Aliaga, R. J.
and Herrero-Bosch, V.
and Capra, S.
and Pullia, A.
and Duenas, J. A.
and Grassi, L.
and Triossi, A.
and Domingo-Pardo, C.
and Gadea, R.
and Gonzalez, V.
and Huyuk, T.
and Sanchis, E.
and Gadea, A.
and Mengoni, D.",
title="Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC",
journal="Nuclear Instruments {\&} Methods in Physics Research A",
year="2015",
publisher="Elsevier Science Bv",
volume="800",
pages="34--39",
optkeywords="Analog memory; Dead time; Detector readout; Front-end electronics; Switched Capacitor Array (SCA); Triggerless data acquisition",
abstract="The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling, Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 $\mu$s window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.",
optnote="WOS:000361878200006",
optnote="exported from refbase (https://references.ific.uv.es/refbase/show.php?record=2407), last updated on Thu, 22 Oct 2015 23:26:41 +0000",
issn="0168-9002",
doi="10.1016/j.nima.2015.07.067",
opturl="https://doi.org/10.1016/j.nima.2015.07.067",
language="English"
}