PT Journal
AU Carrio, F
   Kim, HY
   Moreno, P
   Reed, R
   Sandrock, C
   Schettino, V
   Shalyugin, A
   Solans, C
   Souza, J
   Usai, G
   Valero, A
TI Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
SO Journal of Instrumentation
JI J. Instrum.
PY 2014
BP C03023 - 12pp
VL 9
DI 10.1088/1748-0221/9/03/C03023
LA English
DE Detector control systems (detector and experiment monitoring and slow-control systems; architecture; hardware; algorithms; databases); Data acquisition concepts; Digital electronic circuits
AB The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception.
ER