%0 Journal Article
%T Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench
%A Carrio, F.
%A Kim, H. Y.
%A Moreno, P.
%A Reed, R.
%A Sandrock, C.
%A Schettino, V.
%A Shalyugin, A.
%A Solans, C.
%A Souza, J.
%A Usai, G.
%A Valero, A.
%J Journal of Instrumentation
%D 2014
%V 9
%I Iop Publishing Ltd
%@ 1748-0221
%G English
%F Carrio_etal2014
%O WOS:000336123200023
%O exported from refbase (https://references.ific.uv.es/refbase/show.php?record=1801), last updated on Fri, 20 Jun 2014 10:09:24 +0000
%X The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception.
%K Detector control systems (detector and experiment monitoring and slow-control systems
%K architecture
%K hardware
%K algorithms
%K databases)
%K Data acquisition concepts
%K Digital electronic circuits
%R 10.1088/1748-0221/9/03/C03023
%U https://doi.org/10.1088/1748-0221/9/03/C03023
%P C03023 - 12pp