@Article{Carrio_etal2011,
author="Carrio, F.
and Castillo Gimenez, V.
and Ferrer, A.
and Gonzalez, V.
and Higon-Rodriguez, E.
and Marin, C.
and Moreno, P.
and Sanchis, E.
and Solans, C.
and Valero, A.
and Valls Ferrer, J. A.",
title="Optical Link Card Design for the Phase II Upgrade of TileCal Experiment",
journal="IEEE Transactions on Nuclear Science",
year="2011",
publisher="Ieee-Inst Electrical Electronics Engineers Inc",
volume="58",
number="4",
pages="1657--1663",
optkeywords="High energy physics instrumentation computing; optical-fiber communication high-speed electronics; programmable logic devices",
abstract="This paper presents the design of an optical link card developed in the frame of the R{\&}D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on the hardware design, including signal and power integrity analysis, needed when working with these high data rates and on firmware development to obtain the best performance of the FPGA signal transceivers and for the use of the GBT protocol.",
optnote="WOS:000293975700037",
optnote="exported from refbase (https://references.ific.uv.es/refbase/show.php?record=722), last updated on Fri, 19 Oct 2012 09:40:04 +0000",
issn="0018-9499",
doi="10.1109/TNS.2011.2159125",
opturl="https://doi.org/10.1109/TNS.2011.2159125",
language="English"
}