@Article{Carrio_etal2014,
author="Carrio, F.
and Kim, H. Y.
and Moreno, P.
and Reed, R.
and Sandrock, C.
and Schettino, V.
and Shalyugin, A.
and Solans, C.
and Souza, J.
and Usai, G.
and Valero, A.",
title="Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench",
journal="Journal of Instrumentation",
year="2014",
publisher="Iop Publishing Ltd",
volume="9",
pages="C03023 - 12pp",
optkeywords="Detector control systems (detector and experiment monitoring and slow-control systems; architecture; hardware; algorithms; databases); Data acquisition concepts; Digital electronic circuits",
abstract="The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception.",
optnote="WOS:000336123200023",
optnote="exported from refbase (https://references.ific.uv.es/refbase/show.php?record=1801), last updated on Fri, 20 Jun 2014 10:09:24 +0000",
issn="1748-0221",
doi="10.1088/1748-0221/9/03/C03023",
opturl="https://doi.org/10.1088/1748-0221/9/03/C03023",
language="English"
}