PT Journal
AU Belver, D
   Cabanelas, P
   Castro, E
   Garzon, JA
   Gil, A
   Gonzalez-Diaz, D
   Koenig, W
   Traxler, M
TI Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall
SO IEEE Transactions on Nuclear Science
JI IEEE Trans. Nucl. Sci.
PY 2010
BP 2848
EP 2856
VL 57
IS 5
DI 10.1109/TNS.2010.2056928
LA English
DE Charge to width algorithm; fast amplifying and digitizing electronics; front-end electronics; HADES; time of flight; timing RPC
AB A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m(2) divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel Daughter BOard(DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade [1]. The commissioning of the whole RPC wall is finished and the 6 sectors are already mounted in their final position in the HADES spectrometer and ready to take data during the beam-times foreseen for 2010.
ER